Joseph S. Friedman

Research Summary

I am an assistant professor of Electrical & Computer Engineering at The University of Texas at Dallas and director of the NeuroSpinCompute Laboratory. My research objective is to invent, design, and analyze novel logical and neuromorphic computing paradigms that exploit nanoscale phenomena to achieve greater capabilities than conventional CMOS architectures. In sharp contrast to other proposals for beyond-CMOS and spintronic computing, the central theme of my research is to ensure that individual switching elements can be cascaded and integrated in efficient large-scale information processing systems.

Neuromorphic Computing with Magnetic Domain Walls
Magnetic domain wall neurons and synapses emulate the behavior of neurobiological elements through manipulation of magnetic domain walls. The proposed artificial neurons are the first that intrinsically provide the leaking, integrating, firing, and lateral inhibition capabilities without any additional devices or circuitry. This structure is used to perform handwritten digit recognition with 94% accuracy.
Neural Network Recognition & On-Chip Online Learning with STT-MRAM
This project aims to design and demonstrate an online learning circuit that leverages the stochastic switching of STT-MRAM devices to enable on-chip online learning and recognition.

from Nature Communications 8, 15635 under CC BY 4.0
All-Carbon Spin Logic
In all-carbon spin logic (ACSL), graphene nanoribbons (GNRs) function as spin-diodes connected by carbon nanotubes (CNTs) in accordance with spin-diode logic (SDL). The exceptional properties of low-dimensional carbon, in concert with electromagnetic wave-based signal propagation, provide the potential for Terahertz operation and a 100x improvement in power-delay product.

Reversible Skyrmion Logic
Reversible skyrmion logic leverages magnetic skyrmions in the first nanoscale realization of conservative logic, providing a vision for energy-efficient computation. In this system, magnetic skyrmions propagate through a two-dimensional ferromagnetic structure while performing reversible logic operations at the gate junctions. A simple global clock enables direct cascading with the potential for scalable high-speed low-power reversible Boolean and quantum computing.

Stochastic Bayesian Inference
Bayesian inference is a powerful approach for integrating independent conflicting information for decision-making and robotics, performed with limited efficiency by general-purpose computers. Excitingly, Bayesian inference can be performed extremely efficiently through stochastic computing with Muller C-elements. This fault-tolerant circuit structure enables naive Bayesian inference with multiple orders of magnitude decrease in AEDP.

Stateful Memristor Logic
The non-volatility of memristors enables stateful logic, in which bits are encoded as binary resistance states. However, an alaysis of the required control circuit shows that when this overhead circuitry is included, stateful memristor logic is one billion times less efficient than conventional CMOS logic!
Complementary Magnetic Tunnel Junction Logic
Complementary MAgnetic Tunnel junction logic (CMAT) is a spintronic logic family enabling the cascading of MTJ gates. With a complementary structure analogous to CMOS, CMAT provides non-volatile logic that enables non-von Neumann architectures.
Spin-Diode Logic
Spin-diode logic (SDL) is a spintronic logic family in which two-terminal volatile magnetoresistive devices can be directly cascaded. This logic family uses the current passing through the spin-diodes as the source of the magnetic field to switch other spin-diodes. Positive and negative magnetoresistance devices can be cascaded in this manner to realize large-scale computing systems.

Four-Gate FET Threshold Logic
Threshold logic permits the efficient computation of complex multi-input functions, but the noise margins of electronic devices limit the input combinations to the resolution of the device. The recently demonstrated four-gate electrostatically formed nanowires (EFNs) are natural candidates for threshold logic, enabling compact threshold logic circuits.