Joseph S. Friedman


Four-Gate FET Threshold Logic

Threshold logic permits the efficient computation of complex multi-input functions, but the noise margins of electronic devices limit the input combinations to the resolution of the device. The recently demonstrated four-gate electrostatically formed nanowires (EFNs) are natural candidates for threshold logic, enabling compact threshold logic circuits.

EFN Threshold Logic Device

The EFN device is composed of two metal-oxide-semiconductor (MOS) field-effect transistors (FET) and two junction FETs (JFETs) that modulate charge flow between source and drain contacts. The resistance between source and drain is controlled by voltages on these four independent gates. As can be seen in the simulation results shown in the table, several of the states exhibit high resistances greater than 1012 Ω (red), with the others having a low resistance less than 109 Ω (blue).

Defining an input of -3 V as a logical "1" and 0 V as a logical "0", the EFN device can be considered as a threshold device. The device has a threshold of 3, a front gate weight of 2, and a weight of 1 for the three other gates. If the sum of the weights multiplied by their respected input values are greater than the threshold, the EFN device is in its high resistance state; otherwise, it is in the low resistance state.

Four-Gate FET Threshold Logic Circuits

Connected to a pull-up resistor in the NMOS-type structure above, the output voltage is large whenever the EFN is in a conductive state. This threshold behavior can be observed in the table adjacent to the EFN device schematic (above), with binary "1" outputs representing voltages close to 3 V.

The cascaded EFN threshold logic structure is demonstrated in the one-bit full adder circuit (directly above). This circuit consists of five gate stages and is composed of three EFNs, three n-type MOSFETs, and four resistors. The three inputs (A, B, and CIN) are applied to the series EFNs E1 and E2, which function similarly to the threshold gate described above and output COUT+ (+ subscript denotes the range 0 V to 3 V). In order to propagate the signal to another EFN gate, the conventional transistors M1 and M2 create COUT- and ∼COUT- to shift the voltage (- subscript denotes the range -3 V to 0 V).

The propagation of the binary signals and their respective voltage values are shown in the full adder truth table below. Including the devices necessary for cascading, this compact full adder requires only three active EFNs for logic and three additional MOSFETs, compared to 28 MOSFETs in the conventional implementation.

Experimental Realization

In initial experiments, we have demonstrated an EFN threshold device with three-input control of the resistance. As four states each have resistances greater than 2.7x109 Ω or less than 1.1x106 Ω, this device can be interpreted to perform the threshold logic function described by the equation below. This is equivalent to a majority gate, one of the simplest threshold functions; we are currently working on decreasing the back gate oxide thickness to achieve the function shown in simulation.

Related Publications

  1. A. Peled, X. Hu, O. Amrani, J. S. Friedman, Y. Rosenwaks, An SRAM Based on the MSET Device, IEEE Transactions on Electron Devices 66:3, 1262-1267 (2019).
  2. J. S. Friedman, A. V. Sahakian, A. Godkin, A. Henning, Y. Rosenwaks, System and Method for Threshold Logic with Electrostatically Formed Nanowire Transistors, U.S. Patent #10,002,964 (2018).
  3. J. S. Friedman, A. V. Sahakian, A. Godkin, A. Henning, Y. Rosenwaks, System and Method for Threshold Logic with Electrostatically Formed Nanowire Transistors, U.S. Patent #9,728,636 (2017).
  4. J. S. Friedman, A. Godkin, A. Henning, Y. Vaknin, Y. Rosenwaks, A. V. Sahakian, Threshold Logic with Electrostatically Formed Nanowires, IEEE Transactions on Electron Devices 63:3, 1388-1391 (2016).