Joseph S. Friedman


Neural Network Recognition & On-Chip Online Learning with STT-MRAM

This project aims to design and demonstrate an online learning circuit that leverages the stochastic switching of STT-MRAM devices to enable on-chip online learning and recognition.

Background

The human brain is greatly superior to digital systems for learning and recognition tasks, inspiring efforts to create artificial computing machines that mimic the neurons and synapses in the brain. This has led to the development of dedicated hardware approaches in which the neural network is explicitly fabricated in a crossbar of artificial digital synapses and neurons. While chips such as TrueNorth and Loihi have demonstrated the feasibility of implementing synapses and neurons with conventional digital silicon devices, it is expected that the computing efficiency can be further improved by more closely emulating neurobiological hardware.

To use any of these neural network systems for neuromorphic tasks such as recognition, the synapse weights must be set to particular values through a training process. This training process is central to the artificial intelligence provided by neural networks, as it enables the circuit to develop computing capabilities that have not been explicitly programmed through the circuit design process. The ability of online learning systems to develop computing capabilities after circuit deployment requires coordination with analog circuits that implement the learning rule by providing weight-updating electrical stimuli based on system behavior.

Project Description

This research aims to demonstrate a novel CMOS weight-updating circuit for neural network recognition and on-chip online learning with STT-MRAM. This circuit will perform an unsupervised learning rule through which the relative timing of input and output neuron spikes determine the voltages applied to the various synapses. To perform online learning with the STT-MRAM array, a mixed-signal on-chip learning circuit will be designed to update the synapse weights in the memory array. This learning circuit will provide voltage pulses to the memory array that stochastically switch the STT-MRAM devices. The learning circuit will be designed to ensure a functional prototype and provide a route towards robust, low-cost, high-speed, and energy-efficient large-scale neuromorphic systems. The proposed neuromorphic computing system will be the first complete design and demonstration of an on-chip online learning circuit for STT-MRAM.

This research is sponsored by the Semiconductor Research Corporation/Texas Analog Center of Excellence as Task #2810.030.