Joseph S. Friedman

Hardware Security and Trust with Emerging Technologies

Emerging nanotechnologies intrinsically feature three exciting switching phenomena that can be directly applied to hardware security and trust without requiring any hardware overhead: stochasticity, polymorphism, and non-volatility. This project aims to leverage these phenomena to develop security and trust solutions based on a wide range of emerging technologies. This is a collaborative project with Yiorgos Makris.

Background

As conventional silicon electronics are vulnerable to violations by bad actors, circuit enhancements and adaptations are necessary to provide security and trust. Unfortunately, however, these enhancements and adaptations require significant hardware overhead that increases the area and decreases the efficiency of the computing system. The potential use of hardware components and systems that intrinsically provide security and trust without any overhead would therefore provide a revolutionary advancement to the field across a wide range of computing applications.

The presence of various combinations of stochasticity, polymorphism, and non-volatility in emerging device technologies has enormous potential applications for true random number generation, PUFs, camouflaging, and IP protection. Furthermore, the analog functionality of many emerging technologies extends the range of applications in which these phenomena can be leveraged. A wide range of emerging technologies are currently being developed, such as spintronics, memristors, and ambipolar devices, each with its own intrinsic functionalities and quirks that can be mapped to challenges in hardware security and trust. When incorporated within a silicon-based computing system or applied to a computing system composed solely of emerging technologies, the phenomena of stochasticity, polymorphism, and non-volatility may provide security and trust in a highly-efficient manner.

Project Description

This project aims to leverage the unique behaviors of emerging technologies that intrinsically solve hardware security and trust challenges. It is expected that, as these technologies natively exhibit stochasticity, polymorphism, and non-volatility, they will be highly effective for hardware security and will have minimal hardware overhead. A wide variety of emerging switching phenomena will be mapped to security and trust challenges. Methods will be proposed to exploit these mappings, and circuits will be designed to efficiently implement these methods. Finally, the effectiveness of these solutions and their associated hardware costs will be evaluated in order to indicate which technologies are most promising and to shine light on the applications of these technologies in practical computational circuit applications.

Related Publications

  1. J. D. Arzate, A. N. Chin, Y. Makris, A. J. Edwards, J. S. Friedman, Physically Secure Hardware Redaction with Strain-Shielded Nanomagnetic Logic, Government Microcircuit Applications & Critical Technology Conference, Mar. 2024.
  2. D. Biswas, S. R. Evans, M. J. Rickard, A. Fowler, Y. Makris, N. Hassan, A. J. Edwards, J. S. Friedman, Hybrid MRAM/SRAM Bit Cell with Self-Terminating MTJ Readout, Conference on Magnetism and Magnetic Materials, Oct.-Nov. 2023.
  3. A. N. Chin, J. D. Arzate, Y. Makris, N. Hassan, A. J. Edwards, J. S. Friedman, Hybrid Hardware Security Systems with Strain-Modulated Magnetic Anisotropy, Conference on Magnetism and Magnetic Materials, Oct.-Nov. 2023.
  4. A. N. Chin, J. D. Arzate, Y. Makris, N. Hassan, A. J. Edwards, J. S. Friedman, Physically Secure Hardware Redaction and Logic Locking with Hybrid Logic Systems, Government Microcircuit Applications & Critical Technology Conference, Mar. 2023.
  5. S. R. Evans, M. J. Rickard, A. Fowler, Y. Makris, N. Hassan, A. J. Edwards, D. Biswas, J. S. Friedman, Non-Volatile Memory Circuit with Self-Terminating Read Current, Government Microcircuit Applications & Critical Technology Conference, Mar. 2023.
  6. A. J. Edwards, N. Hassan, D. Bhattacharya, M. M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. S. Friedman, Strain-Modulated Magnetic Anisotropy for Physically Secure Logic Locking, Conference on Magnetism and Magnetic Materials, Oct.-Nov. 2022.
  7. N. Hassan, A. J. Edwards, D. Bhattacharya, M. M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. S. Friedman, Secure Logic Locking with Hybrid CMOS-Nanomagnet Logic, SPIE Spintronics, Aug. 2022 (invited).
  8. A. J. Edwards, N. Hassan, D. Bhattacharya, M. M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. S. Friedman, Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits, Design, Automation & Test in Europe, Mar. 2022 (invited).
  9. A. J. Edwards, N. Hassan, D. Bhattacharya, M. M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. S. Friedman, Physically Secure Logic Locking with Hybrid CMOS-Nanomagnet Logic, Government Microcircuit Applications & Critical Technology Conference, Mar. 2022.
  10. A. J. Edwards, N. Hassan, D. Bhattacharya, M. M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. S. Friedman, Physically and Algorithmically Secure Logic Locking with Hybrid CMOS-Nanomagnet Logic, APS March Meeting, Mar. 2022.
  11. N. Hassan, A. J. Edwards, D. Bhattacharya, M. M. Shihab, V. Venkat, P. Zhou, X. Hu, S. Kundu, A. P. Kuruvila, K. Basu, J. Atulasimha, Y. Makris, J. S. Friedman, Secure Logic Locking with Strain-Protected Nanomagnet Logic, Design Automation Conference, Dec. 2021.


This research is sponsored by the National Science Foundation Industry-University Cooperative Research Center: Center for Hardware and Embedded Systems Security and Trust.