Kanad Basu
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Assistant Professor ContactOffice: ECSN 4.922 |
Education
Ph.D.: Computer Engineering, University of Florida, 2012.
M.S.: Computer Engineering, University of Florida, 2012.
B.E.: Electronics and Telecommunication Engineering, Jadavpur University, India, 2007.
Experience
Assistant Professor, Department of ECE, UT Dallas, August 2019 – present.
Assistant Research Professor, Department of ECE, New York University, September 2017 – July 2019.
Senior R&D Engineer, Synopsys Inc., September 2013-August 2017.
Staff R&D Engineer, IBM Inc., August 2012-August 2013.
News
09/24: Paper titled “Efficient Explainable Boosting Machine for RF Active Metasurface Array Synthesis” has been accepted for publication at IEEE Radio Wireless Week(RWW) 2025
07/24: Paper titled “QuaSi: A Scalable and Reliable Quantum Simulation-based Equivalence Checking Framework” has been accepted for publication at IEEE International Conference on Quantum Computing and Engineering (QCE24)
07/24: SRC published an article on the research and workforce development efforts of the TIES lab here. Thanks SRC!!
07/24: Chao defended his thesis. Congrats Dr. Lu!! Chao is joining Oakridge National Labs as a post-doctoral researcher.
07/24: Team from the TIES lab won the third prize at HACK@DAC 2024
06/24: Dr. Basu is serving as the Technical Program Co-Chair for ATS 2024
05/24: Paper titled “Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping” has been accepted for publication at Transactions on Machine Learning Research 2024
05/24: Paper titled “PristiQ: A Co-Design Framework for Preserving Data Security of Quantum Learning in the Cloud” has been accepted for publication at ISVLSI 2024
05/24: Paper titled “Machine Learning Intervened RIS-based RF Interference Management For IoT” has been accepted for publication at ISVLSI 2024
05/24: Paper titled “A Survey of Side-Channel Attacks in Superconducting Quantum Computers” has been accepted for publication at ISVLSI 2024
05/24: Dr. Basu wins the Assistant Professor Award at UT Dallas “Jonsson School Faculty Research Awards”.
04/24: Paper titled “Assert-O: Context-based Assertion Optimization using LLMs” has been accepted for publication at ACM Great Lakes Symposium on VLSI
04/24: Paper titled “QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits” has been accepted for publication at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
04/24: Paper titled “SCAR: Power Side-Channel Analysis at RTL-Level” has been accepted for publication at IEEE Transactions on VLSI Systems
03/24: Paper titled “System-on-Chip Information Flow Validation under Asynchronous Resets” has been accepted for publication at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
0324: Dr. Basu is serving as a Technical Committee Member for ACMIEEE International Symposium on Low Power Electronics and Design 2024
0324: Dr. Basu is serving as a Technical Committee Member for The International Conference on HardwareSoftware Codesign and System Synthesis (CODES+ISSS) 2024
02/24: Paper titled “Explainability to the Rescue: A Pattern-Based Approach for Detecting Adversarial Attacks” has been accepted for publication at IEEE International Symposium on Hardware Oriented Security and Trust
02/24: Dr. Basu is serving as a Publication Chair for The First IEEE International Workshop on LLM-Aided Design (LAD’24)
02/24: Paper titled “MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks” has been accepted for publication at DAC 2024
0224: Paper titled “Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of EE Systems” has been accepted for publication at DAC 2024
02/24: Paper titled “NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance” has been accepted for publication at DAC 2024
02/24: Dr. Basu is serving as a Special Session Chair for ACM Great Lakes Symposium on VLSI 2024
02/24: Dr. Basu is serving as a Technical Committee Member for International Joint Conference on Neural Netork 2024
01/24: Paper titled “QuBEC: Boosting Equivalence Checking for Quantum Circuits with QEC Embedding” has been accepted for publication at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
01/24: Paper titled “QuEST: Quantum Circuit Output Estimation using Gaussian Distribution Analysis” has been accepted for publication at IEEE International Symposium on Quality Electronic Design
01/24: Paper titled “RASH: Reliable Deep Learning Acceleration using Sparsity-based Hardware” has been accepted for publication at IEEE International Symposium on Quality Electronic Design
01/24: Paper titled “A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans” has been accepted for publication at IEEE International Symposium on Quality Electronic Design
12/23: Paper titled “Analyzing and Mitigating Circuit Aging Effects in Deep Learning Accelerators” has been accepted for publication at IEEE VLSI Test Symposium 2024.
11/23: Paper titled “RTL-Spec: RTL Spectrum Analysis for Security Bug Localization” has been accepted for publication at IEEE International Symposium on Hardware Oriented Security and Trust
11/23: Paper titled “QNAD: Quantum Noise Injection for Adversarial Defense in Deep Neural Networks” has been accepted for publication at IEEE International Symposium on Hardware Oriented Security and Trust
11/23: Congrats Xingyu for defending your PhD thesis. Congrats Dr. Meng. Xingyu is the third PhD graduate from TIES lab.
11/23: Paper titled “Hardware-based Detection of Malicious Firmware Modification in Microgrids” has been accepted for publication at International Conference on VLSI Design
10/23: Paper titled “Real-Time Artificial Intelligence Enhanced Defect Engineering in CeO2 Nanostructures” has been accepted for publication at AVS Journal of Vacuum Science and Technology A.