EEMF 6372 Semiconductor Process Integration

Reading Assignments
Lecture 1: EEMF 6372 Semiconductor Process Integration Syllabus
Lecture 1: EEMF 6372 Semiconductor Process Integration Course Listing
Lecture 2: Process Development Cycle and Organizational Structure
Lecture 2: Transistor Scaling
Lecture 2 Link: Wafer Sizes
Lecture 2: Step-and-Repeat Projection Systems
Lecture 2 Link: Applied Materials
Lecture 2 Link: Applied Materials Endura Avenir RF PVD
Lecture 2 Link: 300 mm Wafer Fabs
Lecture 2 Link: IBM (GlobalFoundries) 300 mm Wafer Fab Main Street Photo
Lecture 2 Link: Intel Fab 32 Video
Lecture 3: Idealized MOSFET Device
Lecture 4: Non-Idealized MOSFET Device
Lecture 5: Device Scaling
Lecture 5 Article: Dennard Device Scaling, Device Scaling: pp. 257-260, Circuit Performance: pp. 264-266
Lecture 5 Article: MOS Transistor Scaling
Lecture 6: CMOS Process Flow
Lecture 6: Self-Aligned Gate Technology
Lecture 6: Planarization Technology
Lecture 6: Photolithography
Lecture 6 Link: Self-Aligned Gate Technology
Lecture 6 Link: Self-Aligned Gate Technology Analysis
Lecture 6 Link: Self-Aligned Gate Technology Milestone
Lecture 6 Link: Self-Aligned Gate Technology Diagrams
Lecture 6 Link: Chemical Mechanical Polishing
Lecture 6 Link: Intel Process Technology History
Lecture 7: Evolution of the MOSFET Device
Lecture 7 Link: International Technology Roadmap for Semiconductors Prior Editions
Lecture 7 Link: International Technology Roadmap for Semiconductors 2015 Edition
Lecture 7 Article: Future MOSFET Device Evolution, pp. 38-39
Lecture 7 Article: Future Industry Directions, Sections 1-2
Lecture 7 Article: Future MOSFET Device Evolution Review
Lecture 7 Article: International Roadmap for Devices and Systems 2016 Edition, More Moore White Paper: pp. 1-15
Lecture 7 Article: International Roadmap for Devices and Systems 2017 Edition, More Moore: pp. 1-21
Lecture 8: Gate Dielectrics: Thin Oxide Films I
Lecture 8: Gate Dielectrics: Thin Oxide Films II
Lecture 8: Thickness Dependence of Direct Tunneling
Lecture 9: High-k Dielectrics and Metal Gates
Lecture 9: Intel CMOS High-k/Metal Gate Process
Lecture 9 Article: High-k Dielectrics and Metal Gate Review, Sections I-III: pp. 8-14.
Lecture 9 Article: Process Integration of Intel High-k Dielectric and Metal Gates
Lecture 9 Article: Intel High-k Dielectrics and Metal Gates I
Lecture 9 Article: Intel High-k Dielectrics and Metal Gates II, Sections 1-2
Lecture 9 Article: Intel CMOS High-k/Metal Gate Process Description
Lecture 9 Article: Sony CMOS High-k/Metal Gate Process Description
Lecture 9 Article: IBM NMOS High-k/Metal Gate Process Description
Lecture 9 Article: IBM CMOS High-k/Metal Gate Process Description
Lecture 10: Strained Silicon
Lecture 10 Article: Strained Silicon Review
Lecture 10 Article: Strained Silicon Process Matrix
Lecture 10 Article: Strained Silicon Intel Technology
Lecture 10 Article: Strained Silicon Intel Gate Last Process
Lecture 11: Deep Submicron MOSFETs
Lecture 12: Raised Source/Drain Structures
Lecture 12 Article: Intel Raised Source/Drain
Lecture 12 Article: NEC Raised Source/Drain
Lecture 12 Article: Toshiba Raised Source/Drain
Lecture 13: Polycides and Salicides
Lecture 13 Article: NiSi Review
Lecture 13 Article: FinFET TiSi
Lecture 14: Shallow Trench Isolation
Lecture 15: Silicon-on-Insulator Technology
Lecture 16: Partially and Fully-Depleted SOI
Lecture 16 Article: IBM Partially-Depleted SOI 32 nm Process
Lecture 16 Article: IBM Partially-Depleted SOI Gate-First Processes
Lecture 16 Article: IBM Partially-Depleted SOI NMOS Gate-First Process
Lecture 16 Article: IBM Partially-Depleted SOI SiGe Threshold Voltage Shift
Lecture 16 Article: IBM Partially-Depleted SOI SiGe Technology
Lecture 16 Article: IBM Partially-Depleted SOI 22 nm Process
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI 32 nm Process
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI and Hybrid Bulk Process
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI Multi-VT and Back Biasing Technology
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI Workfunction Engineering for Multi-VT Technology
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI Technology for the 20 nm Node and Beyond
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI 28 nm Technology Node
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI 14 nm Process
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI 14 nm SiGe Process
Lecture 16 Article: STMicroelectronics Fully-Depleted SOI 14 nm SiGe STI Last Process
Lecture 16 Article: GlobalFoundries Fully-Depleted SOI 22 nm Technology Node
Lecture 16 Article: GlobalFoundries Fully-Depleted SOI 22 nm RF Characteristics
Lecture 16 Link: GlobalFoundries Fully-Depleted SOI Technology
Lecture 17: Tri-Gate Transistors
Lecture 17 Link: Intel Tri-Gate Transistor 22 nm Technology Node
Lecture 17 Link: Intel Tri-Gate Transistor 22 nm Technology Node Presentation
Lecture 17 Article: IBM Tri-Gate Transistor Technology
Lecture 17 Article: Toshiba/IBM/Freescale/AMD FinFET SRAM Cells
Lecture 17 Article: Tri-Gate Versus FinFET Transistor Technology at 15 nm Node
Lecture 17 Article: FinFET AC Performance
Lecture 17 Article: Intel Tri-Gate Transistor 22 nm Technology
Lecture 17 Article: Intel Tri-Gate Transistor 22 nm SoC Technology
Lecture 17 Link: Intel Tri-Gate Transistor 22 nm Construction Analysis 01
Lecture 17 Article: Intel Tri-Gate Transistor 22 nm Construction Analysis 02, Section III 22-nm Transistors, pp. 435-438
Lecture 17 Article: Intel Tri-Gate Transistor 14 nm Technology
Lecture 17 Article: Solid-Source Punch-Through Stopper Doping 14 nm Technology
Lecture 17 Article: Tri-Gate Transistors of Other Manufacturers at 14 nm Technology Node
Lecture 17 Article: Intel Tri-Gate Transistor 10 nm Technology Symposium
Lecture 17 Article: Intel Tri-Gate Transistor 10 nm Technology Paper
Lecture 17 Link: Intel Tri-Gate Transistor 10 nm Technology Analysis
Lecture 17 Article: Samsung Tri-Gate Transistor 7 nm Technology Paper
Lecture 17 Link: Tri-Gate Isolation Concerns - Bulk Versus SOI
Lecture 17 Presentation: Tri-Gate Isolation Concerns - Bulk Versus SOI
Lecture 18: Multilevel Interconnects
Lecture 18 Link: Air-gaps in Copper Interconnects for Logic
Lecture 18 Article: Intel Air Gap Technology
Lecture 18 Article: Self-Aligned Via Process
Lecture 18 Article: Self-Aligned Contact Process
Lecture 18 Article: Self-Aligned Gate Process and Cobalt Metallization
Lecture 18 Link: Cobalt Metallization Process