Summary- Through a collaboration between Dr. Satwik Rajaram's Lab at UTSW and our lab at UTD, we aim to use advanced machine learning techniques to identify which among the virtually infinite range of potential tissue properties (size, shape, organization, etc.) can improve diagnostic predictive power. The key tasks include the following: (i) At UTSW, Dr. Rajaram's lab will obtain various tissue images for analysis. At UTD, we develop the analysis approaches on these images. Specifically, (a) we use deep learning classifiers to identify different tissue states (e.g. nuclear grades, cell types and architectures), (b) analyze data to relate the occurrence patterns of these states to genomic, molecular and/or clinical readouts, and (c) visualize data and results to help interpret and improve these analyses.
Summary- Navigation around an organ during surgery is not an easy task as the visual view is not always reliable. Visual clarity is often limited due to existence of blood and fat tissues. Also, every case and every organ is unique in terms of size, shape, location, etc. In particular, 10-20% of the open heart surgery cases, surgeons have difficulty locating the exact blood vessel with the blockage. Our proposal is to design an imaging system that helps surgeons to navigate easier and more accurately around heart especially during bypass surgeries. Our twin goals will be to: (a) find/design a small set of markers (e.g. colored and/or RFID-based) that provide a clear indication of their positions, and (b) use the markers and a hand-held device to produce the 3D image of the organ with a millimeter-accurate tracing of the markers and device. Achieving these goals will require design of markers, a navigational hand-held device and the use of image processing techniques to overlay a pre-recorded X-ray (or MRI) image with real-time images from a camera during surgery. The lead PI on the team is Dr. Mehrdad Nourani, Electrical Engineering faculty at UTD. The two co-PIs are Dr. Kambiz Alavi, Professor and Associate Chair, Department of Electrical Engineering, The University of Texas at Arlington who is an expert in biometric sensor/detector devices and Dr. James B. Park who is a surgeon and an interventional cardiologist.
Summary- The team consists of a faculty of Electrical Engineering (Prof. Mehrdad Nourani-UTD with expertise in microelectronics and embedded system design), a faculty of Integrative Physiology at the University of North Texas Health Science Center (UNTHSC) (Prof. Michael Smith-UNT with expertise in neural control mechanisms and cardiovascular physiology) and Dr. Jay H. Harvey the medical director of the Epilepsy Center, specialized in neurological disorders and epileptic seizures (THR-Presbyterian Hospital). The focus of this proposal is to develop devices, systems, methods and algorithms that will serve as the basis for efficient monitoring and prediction of epileptic seizures in high-risk patients. Our goal is to use innovative technology to prototype a wrist-worn self-contained system. The proposed system will consist of sensors with peripheral and computational electronics that will (a) continuously measure several potential seizure predictors: heart rate variability (HRV), electrodermal activity (EDA), accelerometry, temperature, and oxygen saturation (SpO2), and (b) utilize signal processing and machine intelligence to monitor and profile a person's physiology, and enable detection of a pre-ictal state in epilepsy patients suffering from intractable seizures.
Summary- The goal of this SBIR project, in general, is to build an analytic system that enhances understanding of the patient's body pressure characteristics, such that it can provide assistive support to care-givers to prevent pressure ulcer. More specifically, we'll use signal/image processing techniques and machine learning approaches to complete the prototype of a software platform for monitoring, prevention and management of pressure ulcers. These analytics include (i) time-stamped whole-body pressure distribution data (image) collection, enhancement and profiling; (ii) posture classification and limb tracking; (iii) quality of turn and risk assessment; and (iv) turning schedule for pressure ulcer management. This project is currently done in Dena Technologies, Inc. a spin-off of University of Texas at Dallas founded in 2011 where Mehrdad Nourani is the President & CEO.
Summary- The reliability tools and design flows currently used in industry, e.g. for NBTI/HCI simulation and lifetime prediction, have limited accuracy and capacity. Consequently, overdesign is often used as a conservative remedy to achieve high reliability and yield. We proposed this project to efficiently grade reliability of MOS transistors in a circuit by using available design tools more judiciously and in a guided framework. This approach will lead to a systematic design-for-reliability approach that avoids the drawbacks of overdesign especially in terms of product cost. Through close collaboration with CMOS Development Reliability Group in Texas Instruments (John Carulli and Kenneth Butler), we plan to: (i) examine the existing design-for-reliability analysis and flow based on Cadence RelXpert tool, (ii) analyze a few case studies to show how overdesign could have been avoided and (iii) propose a reliability evaluation mechanism for MOS transistors that performs more accurate sensitivity classification, runs faster and limits overdesign to devices for which other less costly stress-lowering remedies would not work.
Summary- We propose a novel platform that thoroughly analyzes the network traffic behavior in terms of common substrings to identify potential internet threats. The main idea is to use a two-phase hashing system and small memory units functioning in parallel to achieve a high-throughput and memory efficient behavioral analysis engine. Our system performs behavioral analysis on selected information/user(s) and builds a bell-shaped curve for normal traffic using parallel counters. The system can practically achieve zero false positives and negatives when setting the threshold value based on traffic's historical profile to identify the abnormalities. This type of network behavior analysis is of high demand and interest as it can be employed for security against blended threats in some of the most recent technologies including zero-day worm detection, mobile phones, in-vehicle connectivity, and social (ad-hoc) networks. Our platform can be fine-tuned for various applications (e.g. heart beat cardiac behavior) in which irregularity/abnormality detection to issue early warning is critical.
Summary- The lead principal investigator in Quality of Life Technology (QoLT) Laboratory. The team consists of a faculty of Electrical Engineering (Prof. Mehrdad Nourani-UTD with expertise in microelectronics and embedded system design), two faculty of Electrical Engineering (Prof. Zeynep Butler and Prof. Donald Butler UTA with expertise in MEMS sensors) and Dr Sabatino Bianco, a neurosurgeon doctor specialized in hydrocephalus and CSF shunt implants (THR-Memorial Hospital). In this proposal, we address these two key technological challenges: (i) how to sense the fluid flow in two sides (proximal and distal catheters) of the shunt and (ii) how to sample, record and send data to a reader device wirelessly for monitoring. Microelectromechanical Systems (MEMS) technology will be used in the first task to design and implement such unique sensing devices capable of detecting low levels of flow and clogging without interrupting the normal operation of the shunt. In the second task, we intend to design a very small and ultra low-power proof-of-concept board that can collect and store data samples and deliver it wirelessly to a wireless reader for further processing and decision making.
Summary- In this work, we intend to expand our earlier collaboration with Docomo Communications to design and implement a system that collects data from six sensors (three gyros and three accelerometers). Specifically, this system has two mode of operations: (i) transfer the data stream captured by the six sensors through the USB port and show data real-time on the PC screen and (ii) store data in an on-board SD memory card for post-capture data analysis.
Summary- The lead principal investigator in Quality of Life Technology (QoLT) Laboratory. Other co-PIs are Dr. Alan Bowling (Dept. of Mechanical Eng., UT Arlington), Dr. Deborah Behan (Nurse Researcher, UTA and Texas Health Harris Methodist Hospital) and Dr. Susann Land (MD, Texas Health Harris Methodist Hospital Hurst-Euless-Bedford). In this project we develop the core mechanism of a smart bed that will monitor body pressure and intervene at an early stage to prevent pressure ulcers (PUs). It also incorporates passive means for reducing shear stresses in the skin that contribute to ulcer formation. Our proposed system is a sensor-actuator network with embedded computation and intelligence. It is an intelligent system by virtue of its ability to both sense conditions indicative of the onset of PUs and to intervene autonomously to modify a patient's environment to ameliorate these conditions.
Summary- Collaborated with Dr. Hlaing Minn, we proposed to evaluate various boards (e.g. boards with accelerometers) for their cell phone platforms for customer use in general and personal healthcare applications in particular. While the scope of this project is limited at this time, it will be a great learning tools for us to gain knowledge of the practical platform of advanced cell phones and have access to various chips/boards for experimentation. We intend to use this as a warm up project for the next phase of proposing a larger size joint project.
Summary- The main contribution of this project is a methodology to design scalable and flexible multi-search per cycle routing engines based on a partitioned TCAM architecture. Our two-stage architecture will work effectively for dynamic and unpredicted Internet traffic. The first stage targets the design of a small and flexible lookup shortcut table that works similar to the prefix cache. The shortcomings of the current state of the art are alleviated by storing the prefixes directly with no need for routing table preprocessing. With the completion of this stage, we will have a small but efficient shortcut table that can be duplicated inside a search engine with negligible cost overhead. The outcome of this stage will then be used to augment the partitioned search engine in the next stage. The goal of the second stage is to exploit the inherent parallelism of partitioned TCAM search engines to improve throughput by searching multiple partitions simultaneously. We plan to reach this goal even for dynamic and unpredictable incoming traffic patterns. This is achieved by avoiding contentions using small shortcut table units that accompany block selectors. This shortcut tables dynamically store the most popular prefixes, which are the cause of most contentions. The resulting parallelism that comes at negligible cost, also allows multi-threaded network processors to reduce the number of wait states in their search code pass and further improve the advantage of hardware-based search engines over software search algorithms.
Summary- As we approach 100nm technology, the impact of interconnect on signal integrity is becoming one of the main concerns in testing gigahertz system-on-chips (SoCs). Voltage distortion (noise) and delay violations (skew) contribute to signal integrity loss and ultimately functional error, performance degradation, shorter life and reliability problems. This research proposes a methodology to model and test signal integrity in deep-submicron high-speed interconnects that bind the internal cores in a SoC. The following issues are being explored: (a) the development of a unified integrity fault model, independent of technology, that includes various problems occurring on the SoC's high-speed interconnects such as crosstalk, overshoot, skew, etc.; (b) the establishment of a test generation technique that finds test patterns to stimulate maximal (worst case) integrity loss on the interconnect network; (c) the implementation of noise detector (ND) and skew detector (SD) cells, to detect noise and skew violations (integrity loss) over a period of operation; and (d) the design of a cost- and time-efficient readout architecture to transfer the integrity information that ND and SD cells accumulate. As part of educational plan, we are: 1) developing a two course sequence on ASIC/SoC design and test with emphasis on high-frequency issues; 2) involving undergraduate students in general, and minorities in particular, in VLSI/ASIC/SOC test research. 3) advocating for greater CAD tool use in early stage of CE/EE curriculum.
Summary- Rapid growth of Internet has created a challenge for communication engineers to address the data packet-based routing problem. Packet routing is the chosen communication strategy in many applications such as Internet and wireless networks. Routing is a multi-dimensional problem that requires innovative solutions in different levels of design hierarchy including algorithmic, logic, system and VLSI levels. In this work we investigate a novel router-on-chip (RoC) design to satisfy the Internet's huge appetite for large routing tables, increased traffic, higher speed and the migration to the IPv6 format. Three main objectives in this project are: 1) programmability, 2) flexibility and 3) high-speed. the first two objectives are partially realized by an efficient IP routing methodology and architecture. This is achieved by partitioning the lookup table into the smaller ones for each output port and allowing a routing engine to process them in parallel. This effectively reduces the complexity of finding ``the longest prefix match'' problem to ``a prefix match'' problem. Moreover, it significantly alleviates the need for a large/slow switch fabric and its controller that in many router designs have become the bottleneck. The second and third goals are realized by integrating various cores (e.g. IP router engine, partitioned memory modules, etc.) within a programmable system-on-chip. We estimate that the VLSI implementation of such chip, called router-on-chip (RoC), using 0.25 u m or better technology easily provides aggregated transfer rate of 2.5 Terabit per second that is equivalent to 64 OC-768 or 256 OC-192. From design point of view, this project addresses one of the main challenges in high-speed packet-based communication. High speed routing applications such as telecommunication, satellite communication and ultra-speed Internet networking can immensely benefit from this architecture.
Summary- The primary objective of this research is to design energy efficient VLSI circuits and architectures for applications in telecommunications and digital signal processing (DSP). With the growing popularity of battery powered portable applications like personal communication systems, wireless/mobile computing etc., high performance circuits that dissipate less power (energy efficient) are gaining importance. This research explores two new revolutionary techniques, i.e. (i) Adiabatic Logic and (ii) vMOS (neuron-MOS) based Threshold Gate, at the transistor and gate levels. Using these techniques we will design some widely-used communication cores, study tradeoffs among power, speed and area; and compare the results with traditional low-power CMOS design techniques. We concentrate on the design of basic building blocks for communications and DSP systems. These basic building blocks can be used in conjunction with DSPs to implement widely-used algorithms in hardware. The aim of this project will be to implement critical building blocks of the third generation wireless communications systems (in particular, CDMA systems) which cannot be implemented using DSP architectures. In particular, ACS (Add-Compare-Select), often used in conventional butterfly structure, are the most power-hungry macrocell in many of communication systems such as coding and decoding blocks, the PN code acquisition and tracking, high-speed channel estimation blocks, etc.