The DARClab is composed of the following members


Academic Staff


Dr. Benjamin Carrion Schaefer (Associate Professor)

Graduate Students

Md Imtiaz Rashid (PhD candidate 2020 - UTD) - Modernizing HW Assets
Qilin Si (PhD candidate 2020- UTD) - Design and Optimization of Behavioral ASIPs
Sai Kumar Marri (PhD candidate 2021- UTD) - Optimization of Complex Behavioral SoCs
Chaitali Gajanan Sathe (PhD candidate 2021 - UTD) - Hardware Security
Baharealsadat Parchamdar (PhD candidate 2021 - UTD) - Domain Specific Architecture design

Dearly Departed


Prattay Chowdhury (PhD UTD, 2022) - From Single Component to System-Level Approximate Computing.
Zi Wang (PhD UTD, 2021) - Efficient High-Level Synthesis Design Space Exploration.
Bo Hu (PhD UTD, 2021 - UTD, co-supervised Prof. C. Sechen) - Thermal-aware Placement and High-Level Synthesis for Hardware Security.
Anjana Balachandran (PhD PolyU, 2020) - On the Robustness of Behavioural Circuit Design: From Fault-Tolerance to Hardware Security.
Jianqi Chen (PhD UTD, 2020) - Leveraging the Advantages of High-level Synthesis: From Hardware Security to Low-power Design.
Zhiqi Zhu (PhD UTD, 2020) - Reducing the Complexity of Fault-tolerant HW Accelerators.
Farah Naz Taher (PhD UTD, 2019) - Fault Tolerance in HW Accelerators: Detection and Mitigation.
Siyuan Xu (PhD UTD, 2019) - Towards Robust Approximate Computing.
Shuangnan Liu (PhD PolyU, 2019) - Design and Optimization of Behavioral Data Flows.
Anushree Mahapatra (PhD PolyU, 2018) - On Abstraction Methodologies for RTL-based VLSI Designs to Maximize High-level Synthesis Design Space Exploration and Applications.
Nandeesh Veeranna (PhD PolyU, 2017) - Behavioral Intellectual Property (BIP) Protection.
Yidi Liu (MPhil, PolyU 2015) - Multi processes HW accelleration. HW/SW Co-design.

Valliyappan Senthilkumar (MS UTD, 2023) - ANN Design and Optimization
Amir H. Torabi (MS UTD, 2023) - Automatic Measuring the Quality of HLS
Santosh Shetty (MS UTD, 2020) - Behavioral SoC Generation.
Akshay Raju Krishnani (MS UTD, 2020) - In-situ Implementation and Training of CNNs on FPGAs.
Yiheng Gao (MS UTD, 2020) - Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation.
Rohit Sreekumar (MS UTD, 2020) - Bespoke Behavioral Processor.
Himanshu Patra (MS UTD, 2019) - Behavioral Language Converters to improve HLS Quality of Results.
Maheshwaran Ramesh Babu (MS UTD, 2019) - FPGA acceleration of Hardware Diversity Computation.
Songseok Choi (MS UTD, 2018) - Automating FPGA-based Hardware Acceleration.
Vinay Nagarad Dasavandi Krishnamurth (MS UTD, 2018) - Approximate Computing through bitwidth Optimization.
Monica Jayasheel Gowda (MS UTD, 2018) - High-Level Synthesis Design Space Exploration.
Mihir Shah (MS, UTD, 2018)- Flexible Partial Reconfiguration Based Design Architecture for Dataflow Computing [pdf]
Susmitha Gogineni (MS, UTD, 2017)- Efficient Hardware Acceleration with OpenCL [pdf]
Siyuan Xu (MSc, PolyU, 2015) - HW/SW Co-design [pdf]
Zhendong Gao (MSc, PolyU, 2015)- Speech visualization using FPGAs [pdf] [video]
Jieshi Chen (MSc, PolyU, 2015) - HW-based feature detection
Yu Li (MSc, PolyU, 2014)-FPGA based gaming console [video]
Xiaotong Li (MSc, PolyU, 2014) - Temperature triggered HW Trojan Detection for BIPs [pdf]

Michael Asher Nelson (UTD, 2017/2018)
Chung Kit Ng (BEng, PolyU, 2016)- Internal FPGA temperature measure and display
Chun To Lam (BEng, PolyU, 2016)- FPGA board peripherals control through GUI
Gordon Yeung (BEng, PolyU, 2016)- FPGA based Artifical Neuronal Network
Ka Kit Kwan (BEng, PolyU, 2016)- Online High-Level Synthesis
Jian Su (BEng, PolyU, 2016)- FPGA based cellular automata
Yujian Xiao (BEng, PolyU, 2016)- High-Level Synthesis Design Space Exploration [video]
Shanqi Lu (BEng, PolyU, 2015)- High-Level Synthesis Design Space Explorer [pdf] [video]
Po Ping Wong (BEng, PolyU, 2015) - HW Acceleration with FPGAs [pdf] [video]
Yingxi Chen (BEng, PolyU, 2015) - Web based High-Level Synthesis [pdf] [video]
Qixuan Zhang (BEng, PolyU, 2015) - FPGA based face detection [pdf] [video]
Yunlei Zhang (BEng, PolyU, 2015) - HW-based Feature Detection [pdf] [video]
Sylvain Chan (BSc, PolyU, 2014)-Personal Management Tool/Eisenhower Matrix
Runming Chen (BEng, PolyU, 2014)-Internal FPGA temperature monitoring


Newcomers' Guide

The following newcomers' guide will help new student better understand the development environment and tools used at the lab [pdf]

Our History

Creation of DARClab.
First research students join the laboratory.
S2Cbench v.1.0 open source benchmarks released.
Twitter and Youtube channel creation.
AS2Cbench open source benchmarks released.
First research student graduates from the lab.
Resources web page created [here].
S3CBench behavioral security benchmark suite released.
From September 2016, the DARClab has moved to UT Dallas, USA [UTD ECE].
S2CBench v.2.0 released.
DARClab graduates first PhD student.
DARClab graduates second PhD student.

HLS DSE framework released (DSEframe v1.0) [Github]. DARClab gradudates first two PhD students from UTD.
The lab moves online due to COVID, but continues with the work.
Three major milestones achieved: 10 PhD students graduated; 100 peer reviewed publications; 1,000 citations reached.
Promoted to associate professor.
highX technologies startup from DARClab founded. HLS Made Easy free textbook published.