Keywords: ANSI-C, SystemC, High-Level Synthesis(HLS), Cycle-accurate simulation models, Design Space Exploration (DSE), Low power design, FPGAs, ASICs

Next course : TBD

The International Technology Roadmap for Semiconductors (ITRS) suggests that by 2020 a 10x productivity increase for designing complex System on Chips (SoCs) is needed. Two main factors are predicted to help achieving this goal. The first is the re-use of components. ITRS estimates that around 90% of the SoCs will be composed of re-used components. Secondly is the use of new design methodologies to raise the level of abstraction i.e. High-Level Synthesis (HLS), also called C-based design.

C-Based design has many advantages compared to traditional RTL design. First, it increases the design productivity, which allows design teams to meet the increasingly stringent time-to-market requirements. Second, the ability to create smaller designs compared to hand-coded RTL due to its ability to maximize resource sharing. Lastly the possibility of generating a set of micro-architectures with different area vs. performance trade-offs without having to modify the original behavioral description, also called Design Space Exploration (DSE) are some of them.

This course is organized by the University of Texas at Dalla's Department of Electrical and Computer Engineering (ECE) DARClab (Design Automation and Reconfigurable Computing).

This lab specializes in C-Based VLSI design for ASICs and FPGAs and have among other things released a SystemC Synthesizable Benchmark suite called S2CBench.

The main course instructor is Dr. Benjamin Carrion Schafer, who prior to joining UTD worked at NEC Corporation as an R&D engineer for their commercial HLS tool CyberWorkBench and who was also responsible for the international training program. This course includes multiple topics covered at the training program.

Course Objectives

This course focuses on C-based design based on High-Level Synthesis, including how to verify these designs and co-verify legacy RTL blocks with newly developed C-based design processes. By the end of the course, the participants should be able to:

• Synthesize ANSI-C descriptions using state of the art commercial High-Level Synthesis tools;
• Convert behavioral Software (SW) descriptions (e.g. ANSI C) into synthesizable ANSI C descriptions, understanding the limitations;
• Differentiate between different scheduling modes (automatic, manual and pipeline mode) in order to be able to synthesize different types of applications i.e. data dominant, control dominant or controller circuits;
• Understand the different design techniques available to improve latency, area and delay in C-based VLSI designs;
• Verify C-based designs including: behavioral simulations, cycle-accurate simulations and RTL simulations using the golden inputs from the untimed behavioral description as inputs;
• Co-verify legacy RTL descriptions and new C-based behavioral descriptions;
• Perform manual and automatic Design Space Exploration (DSE);
• Prototype directly from ANSI-C to an FPGA board;
• Introduction to SystemC;
• Apply C-based hierarchical design methods, including functions, multiple processes and bus structures to synthesize complete HW systems.

Target Participants

This course is mainly targeted at HW designers who want to learn how to synthesize and verify behavioral descriptions given in ANSI-C into RTL. In particular the following groups can benefit from this course:

• HW designers (ASIC or FPGA) currently following a traditional RTL-based VLSI Design methodology (VHDL or Verilog).
• SW engineers who want to accellerate computational intensive applications using FPGAs e.g. banking IT departements for low-latency trading or simulation acceleration.
• R&D engineers/scientists who are interested in new VLSI design methodologies
• Students intersted in deepening their knowledge into VLSI design




Pre-requisites

Knowledge of ANSI-C or any high-level programming language is required. VLSI design experience (RTL Design: VHDL or Verilog) is desirable but not compulsory.

Schedule

The course is predominantly practical. Each class will start describing the theoretical background needed and will then be followed by an extensive laboratory hands-on session. For the laboratory sessions state of the art commercial Electronic Design Automation (EDA) tools will be used.

The clases will start at 9.00am until 12:00pm and restart at 13:00pm until 18:00pm for 2 consequtive days. In order to facilitate the participation of working professionals the course will take place over the weekend (Saturday and Sunday)

Day 1

1. High-Level Synthesis Background (2 hours)
   • Target Architecture
   • HLS main steps: (1) Resource Allocation (2) Scheduling and (3) Binding.
   • Main optimizations (loop pipelining, three height reduction, etc.)
   • HLS constraints: Functional Units, frequency, latency.
   • Main commercial HLS tools review .
2. Lab (6 hours)
   • Convert ANSI-C descriptions into synthesizable C for HW descriptions.
   • Understand different scheduling modes (i.e. manual, automatic, pipeline).
   • Synthesize C descriptions with different constraints (i.e. clock, Functional Units).
   • Perform manual Design Space Exploration modifying (Local attributes, global options and FUs).
   • Verify synthesized circuit creating behavioral models, cycle-accurate models and performing RTL simulations.
   • Perform dynamic equivalence checking between initial untimed C description and RTL.

Day 2

1. High-Level Synthesis Optimizations (2 hours)
   • Parallelization (i.e. function inlining, loops unrolling and pipelining, speculation)
   • Latency improvement (e.g. pipelining, loops, memory ports)
   • Area improvement
   • Delay reduction (e.g. FSM encoding)
2. Lab (6 hours)
   • Create control dominated and controller designs using manual scheduling mode (manually timing the C description).
   • Take C design from behavioral description all the way to an FPGA, prototype the design on an FPGA board.

Location

The course will take place at the he Department of Electrical and Computer Enginneering's VLSI Laboratory at UT Dallas campus in Richardson. Click here for directions.

Facilities

The course will make use of the following state-of-the art EDA tools:

• Altera - Quartus
• Aldec - Riviera-PRO
• NEC - CyberWorkBench
• Xilinx - ISE




Contact information

Deptm. of Electrical Engineering (EIE)
The University of Texas at Dallas
800 W. Campbell Rd.
Richardson, TX 75080, USA

Email: schaferb [at] utdallas [dot] edu

Download a course brochure

 

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