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The aim of this group is to do significant research in the areas of VLSI Design Automation and Reconfigurable Computing. Our goal is finding important problems, formulating the problems systematically, and solving them effectively. The target of our optimizations covers both hardware and software. This includes but is not limited to Electronic Design Automation (EDA) problems such as hardware synthesis problems (from system down to circuit level) and embedded software (compiler, operating system) optimization problems.

We do put a big emphasis on the demonstation of the solutions and aim at releasing the software and hardware implementation to the community. For this we relay heavily on FPGAs, thus, the name of our lab.

Another research direction that we are actively persuing covers the area of Design for Trust (DFT). Especially to protect the intellectual property (IP) from EDA vendors.

The DARClab also offers on an continous bases C-based VLSI design and verification couses. These courses are normally offered as a 2 days prodominantly hands-on intensive weekend course. For more information click here.

DARClab News

HLS Design Space Exploration Framework (DSEFrame) v1.0 released - Feburary 2019

Version 1.0 of a GUI-based High-Level Synthesis DSE framework was just released. DSEframe v1.0 can be downloaded from [Github]

S2Cbench version 2.2 released- Feburary 2018

Version 2.2 of the popular SystemC benchmark suite has been released. The benchmarks can be downloaded from [Resources]

ConTex scholarships for Mexican Students- Becas para estudiantes Mexicanos- January 2017

Mexican students intersted in pursuing PhD studies in the area of reconfigurable computing, computer architecture and EDA at the DARClab are invited to apply through the ConTex program [ConTex info español]

The DARClab moves to The University of Texas at Dallas - September 2016

From September 2016, the DARClab has officially moved to Department of Electrical and Computer Engieering of The University of Texas at Dallas [ECE].

Security Behavioral Synthesis Benchmark suite (S3CBench)- August 2016

A benchmark suite implementing Hardware Trojans in 10 of the Synthesizable SystemC benchmarks from the S2Cbench Benchmark suite with different trigger mechanisms and payloads has been released. They can be downlaoded from the Resources web page.

New open source resources web page - January 2016

The source code of most of the projects done at the DARClab has been made public at a new resources web page. The web page can be accessed from Resources web page. It includes HW trojan in SystemC, an ANN implementation in SystemC, the latest S2Cbench benchmarks and their accelerated version and other projects.

Design Automation and Reconfigurable Computing Laboratory (DARClab)

Welcome to UTD's DARClab. As the name indicates we mainly work on VLSI Design Automation and Reconfigurable Computing (FPGAs) topics