DARClab

 

Publications sorted by type

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Books

 

Books published

[B-1] B. Carrion Schafer, High-Level Synthesis Made Easy, highX technologies, pp.1-135, 2023.
 
All

Book Chapters

 

Book chapters published

[BC-3] N. Veeranna and B. Carrion Schafer, Source Code Obfuscation of Behavioral IPs: Challenges and Solutions, Springer, S. Katkoori and S. A. Islam (Eds.), pp.1-12, 2020.

[BC-2] B. Carrion Schafer and K. Wakabayashi, High Performance Computing using FPGAs, Springer, Vanderbauwhede, Wim; Benkrid, Khaled (Eds.), pp.665-694, 2013.

[BC-1] K. Wakabayashi, B. Carrion Schafer, "High-Level Synthesis from Algorithm to Digital Circuit", Springer, P. Coussy, A. Morawiec (Eds.), XVI, ISBN: 978-1-4020-8587-1, Chapter 7, 2008.

 
Published or accepted for publication

Journal Publications

 

Representative journal publications

[J-40] T. Kaur, J.L. Olvera, B. Carrion Schaefer, A. Corona-Chavez, Identification of lyophilized avocado powder adulteration using the cavity perturbation technique at microwave frequencies, ournal of Microwave Power and Electromagnetic Energy, Taylor & Francis, pp.1-14,2024. [pdf]

[J39] Q. Si and B. Carrion Schafer, MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors, Microprocessors and Microsystems (MICPRO), Elseveier, pp.1-10, 2024.

[J-38] Md Imtiaz Rashid and B. Carrion Schafer, Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis, IEEE Transactions of Computer Aided Design (TCAD), pp.1-9, 2024.

[J-37] T. Kaur, A. Gamez, J.L. Olvera, B. Carrion Schaefer, A. Corona-Chavez, I-TAINTED : Identification of Turmeric Adulteration using the Cavity Perturbation Technique and Technology optimized Machine Learning, IEEE Access, pp.1-11,2023. [pdf]

[J-36] Md Imtiaz Rashid and B. Carrion Schafer, Fast and Inexpensive High-Level Synthesis Design Space Exploration : Machine Learning to the Rescue, IEEE Transactions of Computer Aided Design (TCAD), pp.1-12, 2023.

[J-35] Q. Si, P. Chowdhury R. Sreekumar and B. Carrion Schafer, Application Specific Approximate Behavioral Processor, IEEE Transactions on Sustainable Computing, pp. 1-15, 2022.

[J-34] P. Goswami, B. Carrion Schafer and D. Bhatia, Machine Learning Based Fast and Accurate High Level Synthesis Design Space Exploration: From Graph to Synthesis, Integration, the VLSI Journal, Elsevier, Vol. 88, pp. 116-124, 2022.

[J-33] Z. Wang and B. Carrion Schafer, Learning from the Past: Efficient High-Level Synthesis Design Space Exploration for FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), pp.1-24, 2022.

[J-32] Z. Wang and B. Carrion Schafer, SSSL: Secure Search Space Locking of Behavioral IPs, IEEE Transactions of Computer Aided Design (TCAD), pp.1-10, 2021.

[J-31] Q. Si, S. Shetty and B. Carrion Schafer, Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs, MDPI Electronics, pp.1-15, 2021. [pdf]

[J-30] P. Chowdhury and B. Carrion Schafer, Leveraging Automatic High-Level Synthesis Resource Sharing to maximize Dynamical Voltage Overscaling with Error Control, ACM Trans. Design Autom. Electr. Syst. (TODAES), pp. 1-13, 2021.

[J-29] A. Yadav, S. Xu, B. Carrion Schafer and A. Davoudi, Hardware-assisted Simulation of Voltage-behind-reactance Models of Electric Machines on FPGA, IEEE Transactions on Energy Conversion, pp.1247-1257, Vol.35-3, Sept. 2020.

[J-28] S. Liu, F. Lau and B. Carrion Schafer, Predictive Compositional Method to Design and Re-optimize Complex Behavioral Dataflows, IEEE Transactions of Computer Aided Design (TCAD), pp.2615-2627 Vol.39, Issue 10, October, 2020.

[J-27] B. Carrion Schafer and Zi Wang, High-Level Synthesis Design Space Exploration: Past, Present and Future, IEEE Transactions of Computer Aided Design (TCAD), pp.2628-2639, Vol.39, Issue 10, October, 2020.

[J-26] S. Xu, S. Liu, Y. Liu, A. Mahapatra, M. Villaverde, F. Moreno, B. Carrion Schafer, Design Space Exploration of Heterogeneous MPSoCs with variable Number of Hardware Accelerators, Microprocessors and Microsystems, Springer, Vol. 65, pp.169-179, 2019.

[J-25] S. Xu and B. Carrion Schafer, Towards Self-Tunable Approximate Computing IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, pp.778-789, Vol.27(4) 2019.

[J-24] D. Aledo, B. Carrion Schafer, F. Moreno VHDL vs. SystemC: Design of highly Parameterizable Artificial Neural Networks , IEICE Transactions on Information and Systems, Vol.E102-D, No.3, pp. 1-8, Mar. 2019.

[J-23] A. Mahapatra and B. Carrion Schafer, VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration, Integration, the VLSI Journal, Elsevier, Vol. 64, pp. 1-12, 2019.

[J-22] J. N. Randall, J.H.G. Owen, J. Lake, R. Saini, E. Fuchs, M. Mahdavi, S.O. Reza Moheimi and B. Carrion Schaefer, Highly Parallel Scanning Tunneling Microscope Based Hydrogen Depassivation Lithography, Journal of Vaccum Science & Technology B, AVS, Vol. 36, Issue 6, pp.1-10 2018.

[J-21] A. Mahapatra, Y. Liu and B. Carrion Schafer, Accelerating Cycle-accurate System-level Simulations through Behavioral Templates, Integration, the VLSI Journal, Elsevier, pp. 282-291, Vol. 62, June 2018.

[J-20] S. Xu, B. Carrion Schafer, Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 25, Issue 11, pp.3077-3088, 2017.

[J-19] N. Veeranna and B. Carrion Schafer, S3CBench:Synthesizable Security SystemC Benchmarks for High-Level Synthesis, Journal of Hardware and Systems Security, Vol.1. Issue 2, pp.103-113, Springer, 2017.

[J-18] N. Veeranna and B. Carrion Schafer, Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs, Journal of Hardware and Systems Security, Vol. 1. Issue 1, pp. 56-67, Springer, 2017.

[J-17] B. Carrion Schafer, Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies, ACM Trans. Design Autom. Electr. Syst. (TODAES), Vol. 22, Issue 4, pp. 65:1-65:20, 2017.

[J-16] B. Carrion Schafer, Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs through Automatic Internal Bitwidth Adjustments, IEEE Transactions of Computer Aided Design (TCAD), Volume 36, Issue 1, pp. 97-105, Jan. 2017.

[J-15] N. Veeranna and B. Carrion Schafer, Hardware Trojan detection in Behavioral Intellectual Properties(IPs) using Property Checking Techniques, IEEE Transactions on Emerging Topics in Computing, 2016.

[J-14] B. Carrion Schafer, Probabilistic Multi-knob High-Level Synthesis Design Space Exploration Acceleration, IEEE Transactions of Computer Aided Design (TCAD), Vol. 35, No.3, pp. 394-406, March 2016.

[J-13] B. Carrion Schafer, Tunable Multi-Process Mapping on Coarse-Grain Reconfigurable Architectures with Dynamic Frequency Control, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 24, No.1, pp.324-328, January,2016.

[J-12] B. Carrion Schafer, Source Code Error Detection in High-Level Synthesis Functional Verification, IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 24, No.1, pp. 301-312, December 2015.

[J-11] B. Carrion Schafer, Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support, IEEE Embedded Systems Letters, Volume 7, Number 2, pp 51-55, June,2015.

[J-10] B. Carrion Schafer and A. Mahapatra, S2CBench:Synthesizable SystemC Benchmark Suite for High-Level Synthesis , IEEE Embedded Systems Letters, Vol. 6(3), pp. 53-56, 2014.

[J-9] B. Carrion Schafer and K. Wakabayashi, Machine Learning High Level Synthesis Design Space Exploration, IET Computers & Digital Techniques 6(3), pp. 153-159, 2012.

[J-8] B. Carrion Schafer and K. Wakabayashi, Divide and conquer high-level synthesis design space exploration, ACM Trans. Design Autom. Electr. Syst. (TODAES), 17(3): 29, 2012.

[J-7] B. Carrion Schafer and K. Wakabayashi, Precision Tunable Cycle Accurate Power estimation Method, IET Computers & Digital Techniques, Vol 5, Issue 2, pp 95-103,2011.

[J-6] B. Carrion Schafer and M. Sarrafzadeh, Semi-Automatic Control Unit Generation for Complex VLSI Designs, IPSJ System LSI Design Methodology, Vol.3, pp. 234-243, 2010.

[J-5] B. Carrion Schafer Y. Iguchi, W. Takahashi, S. Nagatani and K. Wakabayashi, Fixed Point Data Type Modeling for High Level Synthesis", IEICE Transactions of Electronics, E93-C No.3 , pp 361-368, March, 2010.

[J-4] B. Carrion Schafer and K. Wakabayashi, Design Space Exploration Acceleration through Operation Clustering, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Volume 29, Issue 1, pp. 153-157, Jan. 2010.

[J-3] B. Carrion Schafer and Taewhan Kim, Temperature Reduction in VLSI Circuits through Logic Replication, IET Computers & Digital Techniques, Volume 3, Issue 1, pp 62-71, January 2009.

[J-2] B. Carrion Schafer and Taewhan Kim, Hotspots Elimination and Temperature Flattening for VLSI Circuits, IEEE TVLSI, Volume 16, Number 11,pp. 1475-1488, November, 2008.

[J-1] B. Carrion Schafer, S.F Quigley, A.H.C Chan, Acceleration of the Discrete Element Method on a Reconfigurable Computer, Computers and Structures, Volume 82, Issues 20-21, pp 1707-1718, August 2004.



 
Published or accepted for publication

Conference Publications

 

Representative conference publications

[96] Md Imtiaz Rashid and B. Carrion Schafer, VeriPy: A Python-Powered Framework for Parsing Verilog HDL and High-Level Behavioral Analysis of Hardware, IEEE Dallas Circuit and Systems conference (DCAS), 1-6, 2024.

[95] B. Parchamdar and B. Carrion Schafer, Investigating the Effect of Hyper-Parameter Settings on Simulated Annealing-based High-Level Synthesis Design Space Exploration, IEEE Dallas Circuit and Systems conference (DCAS), 1-5, 2024.

[94] B. Parchamdar and B. Carrion Schafer, Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue, Design Automation Conference (DAC), 1-6, 2024.

[93] S. Xu and B. Carrion Schafer, Temperature Control through dynamic Approximation, GOMACtech, pp. 1-4, 2024.

[92] S. Shetty and B. Carrion Schafer, Facilitating the Design of complete System-on-Chip through High-Level Synthesis, GOMACtech, pp. 1-4, 2024.

[91] B. Carrion Schaefer and C.G. Sathe, Circumventing Restrictions in commercial High-Level Synthesis Tools, Design, Automation, and Test in Europe (DATE), pp. 1-2, 2024.

[90] Q. Si and B. Carrion Schafer, PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2023.

[89] Q. Si and B. Carrion Schafer, ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2023.

[88] Md Imtiaz Rashid, Amir H. Torabi and B. Carrion Schafer, CERTIFY: Automatic Measuring the Quality of High-Level Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5,2023.

[87] Md Imtiaz Rashid and B. Carrion Schafer, MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR, Design, Automation, and Test in Europe (DATE), pp. 1-6, 2023.

[86] C.G. Sathe, Y. Makris and B. Carrion Schafer, MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS, Design, Automation, and Test in Europe (DATE), pp. 1-6, 2023.

[85] Md Imtiaz Rashid, C. Sathe and B. Carrion Schafer, ROPE: Re-usability Lock of Behavioral Intellectual Property, GOMACtech, pp. 1-5, 2023.

[84] Md Imtiaz Rashid, A.T. Hossein and B. Carrion Schafer, Automatic Modernization of Hardware Assets, GOMACtech, pp. 1-5, 2023.

[83] P. Chowdhury, J. Castro Godinez and B. Carrion Schafer, Approximating HW Accelerators through Partial Extractions onto shared Artificial Neural Networks, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.1-6, 2023.

[82] P. Chowdhury, C. G. Sathe and B. Carrion Schafer, Predictive Model Attack for Embedded FPGA Logic Locking, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) pp. 1-6, 2022.

[81] C.G.Sathe, Y. Makris and B. Carrion Schafer, Investigating the Effect of different eFPGAs fabrics on Logic Locking through HW Redaction, IEEE Dallas Circuits and Systems Conference (DCAS), pp. 1-6, 2022.

[80] Q. Si and B. Carrion Schafer, Optimizing Behavioral Near On-Chip Memory Computing Systems, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 1-7, 2022.

[79] Md Imtiaz Rashid and B. Carrion Schafer, Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2022.(Best Paper Award)

[78] Md Imtiaz Rashid, Qilin Si and B. Carrion Schafer, Modernizing Hardware Circuits through High-Level Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5,2022.

[77] B. Carrion Schafer, Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.1-6, 2022.

[76] Md Imtiaz Rashid and B. Carrion Schafer, Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.1-6, 2022.

[75] Z. Wang, S. O. Mohammed, Y. Markis and B. Carrion Schafer, Functional Locking through Omission: From HLS to Obfuscated Design, IEEE International Conference on Computer Design (ICCD) pp. 1-8, 2021.

[74] P. Chowdhury and B. Carrion Schafer, ADATP: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing, IEEE International Conference on Computer Design (ICCD), pp. 1-4, 2021 (invited paper).

[73] P. Chowdhury and B. Carrion Schafer, BEACON : BEst Approximations for Complete BehaviOral HeterogeNeous SoCs, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) pp. 1-6, 2021.

[72] Q. Si, Md I. Rashid and B. Carrion Schafer, Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 1-6, 2021.

[71] P. Chowdhury and B. Carrion Schafer, Unlocking Approximations through Selective Source Code Transformations, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2021.

[70] S. Shetty and B. Carrion Schafer, Enabling the Design of Behavioral Systems-on-Chip, Design Automation Conference (DAC), pp. 1-6, 2021.

[69] Z. Zhu and B. Carrion Schafer, Reducing the Complexity of Fault-Tolerant System amenable to Approximate Computing, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5,2021.

[68] Y. Gao and B. Carrion Schafer, Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5,2021.

[67] P. Kalimuthu, K. Basu and B. Carrion Schafer, Efficient Hierarchical Post-Silicon Validation and Debug, International Conference on VLSI Design (VLSID), pp. 1-6, 2021. (Honorary Mention Award)

[66] Z. Wang and B. Carrion Schafer, Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions, Design, Automation, and Test in Europe (DATE), pp. 1-4, 2021.

[65] J. Chen and B. Carrion Schafer, Watermarking of Behavioral IPs: A Practical Approach, Design, Automation, and Test in Europe (DATE), pp. 1-6, 2021.

[64] J. Chen and B. Carrion Schafer, Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.1-6, 2021.

[63] M. Shah and B. Carrion Schafer, Flexible Runtime Reconfigurable Computing Overlay Architecture and Optimization for Dataflow Applications, Hierarchical Parallelism for Exascale Computing (HiPar) , pp.1-8, 2020

[62] R. Sreekumar, P. Chowdhury and B. Carrion Schafer, Bespoke Behavioral Processors, IEEE International Conference on Computer Design (ICCD), pp. 1-4, 2020.

[61] A. Balachandran and B. Carrion Schafer, Efficient Functional Locking of Behavioral IPs, IEEE International Midwest Symposium on Circuits and Systems (MWCAS), pp.1-4, 2020.

[60] Z. Wang and B. Carrion Schafer, Machine Learning to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration, Design Automation Conference (DAC), pp. 1-6, 2020.

[59] J. Chen, M. Zaman, Y. Makris, S. Blanton, S. Mitra and B. Carrion Schafer , DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY, Design Automation Conference (DAC), pp. 1-6, 2020.

[58] Z. Zhu and B. Carrion Schafer, Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5,2020.

[57] M. Shihab, J. Tian, G. Rajavendra Reddy, B. Hu, W. Swartz Jr., B. Carrion Schaefer, C. Sechen and Y. Makris, A Transistor-Level Fabric for Design Obfuscation, GOMACTech-20, pp.1-6, 2020.

[56] Z. Wang, J. Chen and B. Carrion Schafer, Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization, Design, Automation, and Test in Europe (DATE), pp. 1-6, 2020.

[55] B. Hu, M. W. Swartz Jr., Y. Makris, B. Carrion Schafer, C. Sechen, An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs , Design, Automation, and Test in Europe (DATE), pp. 1-6, 2020.

[54] S. Xu and B. Carrion Schafer, On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations, Design, Automation, and Test in Europe (DATE), pp. 1-6, 2020.

[53] B. Hu, M. Shihab, W. Swartz Jr., Y. Makris, B. Carrion Schafer, C. Sechen, Extending the Lifetime of Coarse-grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage, International Conference on Field-Programmable Technology (FPT), pp. 1-4, 2019.

[52] F.N.Taher, A. Balachandran and B. Carrion Schafer, Learning-based Diversity Estimation: Leveraging the Power of High-level Synthesis, International Conference on Computer Design (ICCD), pp.1-8, 2019.

[51] J. Chen and B. Carrion Schafer, Low Power Design through Frequency-Optimized Runtime Micro-architectural Adaptation, International Conference on Computer Design (ICCD), pp.1-8, 2019.

[50] J. Chen and B. Carrion Schafer, Exploiting the Benefits of High-level Synthesis for Thermal-aware VLSI Design, International Conference on Computer Design (ICCD), pp.1-4, 2019.

[49] S. Xu and B. Carrion Schafer, Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations , International Conference on Computer Design (ICCD), pp.359-366, 2019.

[C48] S. Xu and B. Carrion Schafer, Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models, IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.1.-8, 2019.

[C47] M.R. Babu, F. N. Taher, A. Balajandran and B. Carrion Schafer, Efficient Hardware Acceleration for Design Diversity Calculation to mitigate Common Mode Failures, IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM), pp.1-4, 2019.

[C46] J. Chen and B. Carrion Schafer, Thermal Fingerprinting of FPGA Designs through High-Level Synthesis, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 331-334, 2019 .

[C45] Z. Zhu, F. N. Taher and B. Carrion Schafer, Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 291-294, 2019.

[C44] B. Hu, J. Tian, M. Shihab, G. R. Reddy, W. Swartz Jr., Y. Makris, B. Carrion Schafer, C. Sechen, Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, 2019.

[C43] S. Liu, F. Lau and B. Carrion Schafer, Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration, Design Automation Conference (DAC), pp. 97:1-97:6, 2019.

[C42] A. Mahapatra and B. Carrion Schafer, Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration, IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, 2019.

[C41] Z. Wang and B. Carrion Schafer, Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis, Design, Automation, and Test in Europe (DATE), pp. 642-645, 2019.

[C40] M. Shihab, J. Tian, G. Rajavendra Reddy, B. Hu, W. Swartz Jr., B. Carrion Schaefer, C. Sechen and Y. Makris, Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming, Design, Automation, and Test in Europe (DATE), pp. 528-533, 2019.

[C39] F. N. Taher, M. Joslin, A. Balachandran, Z. Zhu and B. Carrion Schafer, Common-Mode Failure Mitigation:Increasing Diversity through High-Level Synthesis, Design, Automation, and Test in Europe (DATE), pp. 1563-1566, 2019.

[C-38] Z. Zhu , J. Callenes-Sloan and B. Carrion Schafer, Control Flow Checking Optimization Based On Static Analysis of Regular Patterns IEEE Pacific Rim Symposium on Dependable Computing (PRDC), 2018, pp. 1-10.

[C-37] S. Xu and B. Carrion Schafer, DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures, International Conference on Computer Design (ICCD), pp.587-594, 2018

[C-36] S. Xu and B. Carrion Schafer, Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles, International Conference on Computer Design (ICCD), pp. 346-349, 2018.

[C-35] F. N. Taher, M. Kishani and B. Carrion Schafer, Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis, IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 1-4, 2018.

[C-34] S. Liu, F. Lau and B. Carrion Schafer, Investigation and Optimization of Pin Multiplexing in High-Level Synthesis, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-4, 2018.

[C-33] F. N. Taher, J. Callenes-Sloan and B. Carrion Schafer, A machine learning based hard fault recuperation model for approximate hardware accelerators, Design Automation Conference (DAC), pp. 1-6, 2018.

[C-32] S. Xu, J. Chen and B. Carrion Schafer, HW/SW Co-design Experimental Framework using Configurable SoC, International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.1-6, 2017.

[C-31] S. Xu. Y. Liu, B. Carrion Schafer, Configurable SoC In Situ Hardware/Software Co-Design Design Space Exploration, International Conference on Computer Design (ICCD), pp. 1-3, 2017.

[C-30] S. Xu and B. Carrion Schafer, Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-architecture to Dynamic Workloads, International Conference on Computer Design (ICCD), pp. 1-7, 2017.

[C-29] S. Liu and B. Carrion Schafer, Learning-based Interconnect-aware Dataflow Accelerator Optimization, Field Programmable Logic (FPL), pp. 1-7, Ghent, 2017.

[C-28] B. Carrion Schafer, David Aledo, F. Moreno, Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neuronal Networks. A Case Study, Euromicro Digital System Design (DSD), pp.1-8, 2017.

[C-27] Y. Liu, M. Villaverde, F. Moreno, B. Carrion Schafer, Characterization and Optimization of Behavioral Hardware Accelerators in Heterogeneous MPSoCs, 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp.1-8,2017.

[C-26] M. Yasin, A. Sengupta, B. Carrion Schafer, Y. Makris, O. Sinanoglu and JV Rajendran, What to Lock? Functional and Parametric Locking, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2017.

[C-25] N. Veeranna and B. Carrion Schafer, Efficient Behavioral Intellectual Property Source Code Obfuscation for High-Level Synthesis, 18th IEEE Latin American Test Symposium, Bogota, Colombia, 2017.

[C-24] N. Veeranna and B. Carrion Schafer, Hardware Trojan Avoidance and Detection for Dynamically Re-configurable FPGAs, International Conference on Field-Programmable Technology (FPT), pp. 193-196, 2016.

[C-23] D. Liu and B. Carrion Schafer,Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs, Field Programmable Logic (FPL), Lausanne, 2016.

[C-22] A. Balachandran, N. Veeranna and B. Carrion Schafer,On Time Redundancy of Fault Tolerant C-Based MPSoCs, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, July, 2016.

[C-21] Y. Liu and B. Carrion Schafer,Optimization of Behavioral IPs in Multi-Processor System-on-Chips, Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 336-341, Macao, January, 2016.

[C-20] I. Llamas Garro, J. Bas, J. M Fabrega, B. Carrion Schafer, R. Torres Torres, M.R.T de Oliveira, M.T. de Melo, J-M Kim and D. Vukobratovic,"Recent Trends and Considerations for High Speed Data in Chips and System Interconnects", IEEE International Microwave and Optoelectronics Conference (IMOC), November, pp. 1-6, 2015.

[C-19] X. Li and B. Carrion Schafer,Temperature-triggered Behavioral IPs HW Trojan Detection Method with FPGAs, Field Programmable Logic (FPL), September, 2015.

[C-18] Y. Liu and B. Carrion Schafer,Adaptive Combined Macro and Micro-Exploration of Concurrent Applications mapped on shared Bus Reconfigurable SoC, ESLSyn,San Francisco,2015.

[C-17] B. Carrion Schafer, Process Selection for Maximum Resource Sharing in High-Level Synthesis, ESLSyn, San Francisco,2015.

[C-16] Y. Liu and B. Carrion Schafer,HW Acceleration of Multiple Applications on a Single FPGA, International Conference on Field-Programmable Technology (FPT), pp. 284-285,2014.

[C-15] B. Carrion Schafer,Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process System, International Conference on Field-Programmable Technology (FPT), pp. 76-82, 2014.

[C-14] A. Mahapatra and B. Carrion Schafer, Machine-Learning based Simulated Annealer method for High Level Synthesis Design Space Exploration, ESLsyn,San Francisco,2014.

[C-13] B. Carrion Schafer, Allocation of FPGA DSP-Macros in Multi-Process High-Level Synthesis Systems, Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, pp. 616-621, 2014.

[C-12] B. Carrion Schafer, Automatic Partitioning of Behavioral Descriptions for High-Level Synthesis with Multiple Internal Throughputs", ESLsyn, Austin, 2013.

[C-11] S. Golshan, E. Bozorgzadeh, B. Carrion Schafer, K. Wakabayashi, H. Homayoun, and A. Veidenbaum, Exploiting Power Budgeting in Thermal-Aware Dynamic Placement in Reconfigurable Systems, ISLPED, pp. 49-54, 2010.

[C-10] B. Carrion Schafer, A. Trambadia and K. Wakabayashi, Design of Complex Image Processing Systems in ESL, Asia and South Pacific Design Automation Conference (ASP-DAC), Taiwan, Pages 809 - 814, 2010.

[C-9] B. Carrion Schafer, T. Takenaka, K. Wakabayashi, Adaptive Simulated Annealer for High Level Synthesis Design Space Exploration, VLSI DAT, pp. 106-109, Taiwan, 2009.

[C-8] B. Carrion Schafer, Y. Lee and T. Kim, Temperature-Aware Compilation for VLIW Processors, 13th IEEE International conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), pp 426-431, Daegu, Korea, 2007.

[C-7] B. Carrion Schafer and Taewhan Kim, Thermal-Optimized VLIW Processors Instructions Allocation, 11th Workshop on Interaction between Compilers and Computer Architectures (ITERACT-11), 2007.

[C-6] B. Carrion Schafer, S.F Quigley, A.H.C Chan, Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform, 12th International Conference on Field Programmable Logic and Applications (FPL), Montpellier, 2002.

[C-5] B. Carrion Schafer, S.F Quigley, A.H.C Chan, Implementation of the Discrete Element Method using reconfigurable computing (FPGAs), 15th Engineering Mechanics Conference (EM2002), Columbia University, New York, 2002.

[C-4] B. Carrion Schafer, S.F Quigley, A.H.C Chan, Analysis and Implementation of the Discrete Element method using a dedicated highly parallel Architecture in Reconfigurable Computing, IEEE Symposium on Field- Programmable Custom Computing Machines (FCCM), Napa Valley, California, 2002. IEEE Computer Society,2002.

[C-3] B. Carrion Schafer, S.F Quigley, A.H.C Chan, Description of a Dedicated Hardware Architecture for the Discrete Element Method (DEM) implemented on a Field Programmable Gate Array (FPGA),10th Annual conference of the Association for Computational Mechanics in Engineering (ACME), Swansea, pp 51-54,2002.

[C-2] B.Carrion Schafer, S.F Quigley, A.H.C Chan, Evaluation of an FPGA implementation of the Discrete Element Method (DEM) , 11th International Conference on Field Programmable Logic and Applications (FPL), Belfast, pp 306-314, 2001.

[C-1] B.Carrion Schafer, S.F Quigley, A.H.C Chan, Numeric Modeling of the Mechanical interaction between non-biological particles using reconfigurable computing ,9th Annual conference of the Association for Computational Mechanics in Engineering (ACME), Birmingham, pp 53-56, 2001.



 

Other Publications

 

Non refereed publications, workshops, newsletters and forums

[F-11] P. Chowdhury, Jorge Castro Godinez and Benjamin Carrion Schafer, ANN based Approximation of HW Accelerators , 7th Workshop on Approximate Computing (AxC22), July, 2022.

[F-10] P. Kalimuthu, K. Basu and B. Carrion Schafer, Trace Buffer Bandwidth-aware Post-Silicon Debug, IEEE VLSI circuits & Systems Letter, Vol.7. Issue 2, April 20201.

[F-9] N. Veeranna and B. Carrion Schafer, Automatic Hardware Trojan Insertion in Behavioral IPs during the Obfuscation Process, Design Automation Conference (DAC), Hack@DAC, Austin, 2017 (Third place) [pdf] .

[F-8] B. Carrion Schafer,Approximate Computing: Mitigating the Risk of Dynamic Workloads, IEEE COMSOC Technology News (CTN), 2017 [html].

[F-7] B. Carrion Schafer,HW/SW Co-simulation Integration into High Level Synthesis Flow, MPSoC, Quebec, Canada, June 2012.

[F-6] K. Wakabayashi and B. Carrion Schafer, ESL Synthesis Made Real, ESWeek, 2011, (invited talk).

[F-5] B. Carrion Schafer and K. Wakabayashi, High Level Synthesis Dynamic Equivalence Checker, ICCAD China, 2011 (translated into Chinese).

[F-4] B. Carrion Schafer,Complete C-Based SoC design: Is it possible?, MPSoC, Gifu, Japan, June 2010.

[F-3] B. Carrion Schafer, K. Wakabayashi, Design Space Exploration in High Level Synthesis, DAC (user track), 2010.

[F-2] S. Morioka, B. Carrion Schafer and K. Wakabayashi, Complex Security Engine Design in High Level Synthesis, MPSoC, Savannah, USA, August 2009.

[F-1] B. Carrion Schafer, L. Kumar, K. Wakabayashi, Power Library Pre-Characterization Automation, Design Automation Conference, DAC (user track), 2009.



 

Patents

 

Registered

[PT-2] B. Carrion Schafer, "Method, Design Apparatus, and Program Product for Incremental Design Space Exploration", Patent No. 8,977,996 US, 2015.

[PT-1] B. Carrion Schafer, "Method and Apparatus for Design Space Exploration in High Level Synthesis",Patent No. 2012-522281, JP.



 

Presentations

 

Public presentations and invited talks

[T-6] B. Carrion Schafer "Techniques for Finding Security Vulnerabilities in an SoC ", DAC, San Francisco, (Invited speaker), 2018.

[T-5] B. Carrion Schafer "Behavioral IPs Micro-architectural Diversity and its Applications ", ESLSyn, San Francisco, (Invited speaker), 2015.

[T-4] B. Carrion Schafer and A. Mahapatra "S2CBench:Synthesizable SystemC Benchmark Suite for High-Level Synthesis", 20th meeting of the North American SystemC Users Group,2014 [pdf].

[T-3] B. Carrion Schafer "The ESL Hotspot - Where Software and Hardware Meet", DAC, 10th anual ESL Symposium, San Francisco, (invited panelist), 2012.

[T-2] B. Carrion Schafer "High-Level Synthesis Production Deployment: Are We Ready?", DAC, San Francisco, (invited speaker), 2012.

[T-1] B. Carrion Schafer "Challenges and Opportunities of Behavioral Level SoC Design", ESLSyn, San Francisco, (Keynote speaker), 2012.