/**************************************************************
*	This is main module for state machine of TrafficLight
* Xiangyu Xu
**************************************************************/

module TrafficLight(state, RedLight, GreenLight, YellowLight, clk, reset, malfunction, ready);

  input clk, reset, ready; //ready is high when maintenance of TrafficLight finished
  input malfunction;       //system input malfunction when error occured
  
  output [1:0] state;
  output RedLight,GreenLight,YellowLight; //active-high output for Lights
  reg [1:0] state;        //register to store current state
  reg RedLight,GreenLight,YellowLight;

  //define parameter or name of each state
  parameter redstate = 2'b00;
  parameter greenstate = 2'b01;
  parameter yellowstate = 2'b10;
  parameter maintenance = 2'b11;
 

always@ (posedge clk)
  begin
  RedLight = (!state[1] & !state[0]);
  GreenLight = (!state[1] & state[0]);
  YellowLight = (state[1] & !state[0]);

    if(reset)
      begin
        state = redstate;   //default state is RedLight on
      end
    
    else case(state)  
      
        redstate:
          begin
            if(malfunction)
              state = maintenance;
            else
              state = greenstate;
          end

        
        greenstate:
          begin
            if(malfunction)
              state = maintenance;
            else
              state = yellowstate;
          end                           

        
        yellowstate:
          begin
            if(malfunction)
              state = maintenance;
            else
              state = redstate;
          end                           

        
        maintenance:
          begin
            if(ready)
              state = redstate;
            else
              state = maintenance;
          end                           
            

      endcase
    
  end

endmodule

/**************************************************************
*	This module is for testing and display outputs.
# Xiangyu Xu
**************************************************************/
module test_module;     // declare test module

  reg clk, reset, malfunction, ready;
  wire [1:0] state;
  wire RedLight, GreenLight, YellowLight;
  
  parameter clockDelay = 50;

  TrafficLight    myTrafficLight(state, RedLight, GreenLight, YellowLight, clk, reset, malfunction, ready);

   always
    begin
      #(clockDelay/2) clk = 0;
      #(clockDelay/2) clk = 1;

    end

  initial
    begin
    $dumpfile("Trafficlight.dump");
    $dumpvars;
    $monitor ("stat= %b, RedLight = %b, Green = %b, YellowLight = %b",state, RedLight, GreenLight, YellowLight);
    //$shm_open("db1.shm");  // Open a directory to store waveforms       
    //$shm_probe(state, RedLight, GreenLight, YellowLight, reset, malfunction, ready);      // Specify any signals you want waveforms for
	
	   #(clockDelay) reset = 1'b1;
      #(clockDelay) reset = 1'b0;
      #(clockDelay) malfunction = 1'b1;
      #(clockDelay) reset = 1'b0;            
      #(clockDelay) malfunction = 1'b0;
      #(clockDelay) 
      #(clockDelay) 
      #(clockDelay) ready = 1'b1;
      #(clockDelay)  ready = 1'b0;           
      #(clockDelay) 
      #(clockDelay) 
      #(clockDelay)
      #(clockDelay) reset = 1'b1;
      #(clockDelay) reset = 1'b0;
      #(clockDelay) 
      #(clockDelay) malfunction = 1'b1;
      #(clockDelay) malfunction = 1'b0;
      #(clockDelay) 
      #(clockDelay)             
      #(clockDelay) ready = 1'b1;
      #(clockDelay)  ready = 1'b0; 
      #(80*clockDelay)
              $finish;
    end


endmodule