Yiorgos Makris

• Home
• CV
• Research
• Funding
• Publications
• Presentations
• Activities
• Students
• Teaching

Publications

Patents

1. US 10,511,308 �Field Programmable Transistor Arrays,� Issued Dec. 17, 2019
2. US 10,855,285 Continuation of Application �Field Programmable Transistor Arrays,� Issued Dec. 1, 2020
3. US 11,362,362 Continuation of Application �Field Programmable Transistor Arrays,� Issued Jun. 28, 2022
4. US 11,449,658, �Methods for Generating Integrated Circuit (IC) Layout Synthetic Patterns and Related Computer Program Products,� Issued Sep. 20, 2022
5. PCT/US2021/033108, �Genetic Physical Unclonable Functions and Methods of Use Thereof,� Filed May 18, 2021

Book Chapters

1. S. Jajodia, R. Samarati and M. Yung (Editors), Encyclopedia of Cryptography, Security and Privacy, Springer, 2022 (K. Subramani, A. Antonopoulos, A. Nosratinia and Y. Makris, "Hardware-Induced Covert Channels in Wireless Networks: Risks and Remedies") (invited) (link)
2. A. Elfadel, D. Bonning and X. Li (Editors), Machine Learning in VLSI Computer-Aided Design, Springer, 2018 (N. Kupp, K. Huang, A. Ahmadi, C. Xanthopoulos and Y. Makris, "Gaussian Process-Based Wafer-Level Correlation Modeling and its Applications") (invited) (link)
3. S. Bhunia and M. Tehranipoor (Editors), The Hardware Trojan War: Attacks, Myths, and Defenses, Springer, 2017 (A. Antonopoulos, C. Kapatsori, Y. Makris, "Hardware Trojans in Analog, Mixed-Signal and RF ICs") (invited) (link)
4. C. H. Chang, M. Potkonjak (Editors), Secure System Design and Trustable Computing, Springer, 2015 (Y. Jin, D. Maliuk, Y. Makris, "Hardware Trojan Detection in Analog/RF Integrated Circuits") (invited) (link)
5. T. Noulis, M. Soma (Editors), Mixed-Signal Circuits, CRC Press, 2015 (D. Maliuk, H. Stratigopoulos, Y. Makris, "Machine Learning-Based BIST in Analog/RF ICs") (invited) (link)
6. K. Iniewski (Editor), Advanced Circuits for Emerging Technologies, John Wiley & Sons, 2012 (H. Stratigopoulos,Y. Makris, "Checkers for On-line Self-Testing of Analog Circuits,"� (invited)) (link)
7. M. Tehranipoor, C. Wang (Editors), Introduction to Hardware Security and Trust, Springer, 2011 (Y. Jin, E. Love, Y. Makris , "Design for Hardware Trust," (invited)) (link)
8. L. T. Wang, C. E. Stroud, and N. A. Touba (Editors), System on-Chip Test Architectures, Morgan-Kaufman Publishers, 2007 (Y. Makris, section 8.4,"Circuit-Level Approaches to Soft Error Mitigation," (invited)) (link)

Journal Papers

1. Y. Li, M. Bidmeshki, T. Kang, C. Nowak, Y. Makris, L. Bleris, �Genetic Physical Unclonable Functions in Human Cells.� Science Advances, vol. 8, no. 18, 2022 (link)
2. P. Yelleswarapu, A. Jha, R. Willis, Y. Makris, K. K. O, �Phase Noise Reduction in LC VCO�s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection,� IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 6, pp. 3244-3256, 2022 (pdf)
3. A. Edwards, N. Hassan, D. Bhattacharya, M. Shihab, P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. Friedman, �Physically and Algorithmically Secure Logic Locking with Hybrid CMOS-Nanomagnet Logic,� Bulletin of the American Physical Society, 2022 (link)
4. Y. Li, M. Bidmeshki, T. Kang, C. Nowak, Y. Makris, L. Bleris, �Provenance Attestation of Human Cells Using Physical Unclonable Functions,� bioRxiv 2021.06.11.448108, doi: https://doi.org/10.1101/2021.06.11.448108, 2021, (pdf), (Supplementary Material)
5. L. Zhou, Y. Zhang, Y. Makris, �TPE: A Hardware-Based TLB Profiling Expert for Workload Reconstruction,� IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 11, no. 2, pp. 415-427, 2021 (pdf)
6. M. Bidmeshki, An. Antonopoulos, Y. Makris, �Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs,� IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 11, no. 2, pp. 292-305, 2021 (pdf)
7. G. R. Reddy, C. Xanthopoulos and Y. Makris, �On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement,� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T.CAD), 2021 (to appear) (pdf) � Extended Version Available on arXiv (pdf)
8. J. W. Smith, S. Thiagarajan, R. Willis, Y. Makris and M. Torlak, �Improved Static Hand Gesture Classification on Deep Convolutional Neural Networks Using Novel Sterile Training Technique,� IEEE Access, vol. 9, pp. 10893-10902, 2021 (pdf)
9. K. Liu, B. Tan, G. Rajavendra Reddy, S. Garg, Y. Makris, R. Karri, �Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks,� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), 2021 (to appear) (pdf)
10. M. Bidmeshki, Y, Zhang, M. Zaman, L. Zhou, Y. Makris, �Hunting Security Bugs in SoC Designs: Lessons Learned,� IEEE Design & Test of Computers (D&T), 2020 (pdf)
11. K. S. Subramani, N. Helal, A. Antonopoulos, A. Nosratinia and Y. Makris, "Amplitude-Modulating Analog/RF Hardware Trojans in Wireless Networks: Risks and Remedies," IEEE Transactions on Information Forensics and Security (T.IFS), vol. 15, pp. 3497-3510, 2020 (pdf)
12. C. Xanthopoulos, A. Neckerman, P. List, K.-P. Tschernay, P. Sarson, Y. Makris, �Automated Die Inking,� IEEE Transactions on Device and Materials Reliability (T. DMR), vol. 20, no. 2, pp. 295-307, 2020 (pdf)
13. L. Zhou, Y, Hu, Y. Makris, �A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics,� IEEE Transactions on Computers (T. COMP), vol. 69, no. 11, pp. 1668-1680, 2020 (pdf)
14. Y. Zhang, L. Zhou, Y. Makris, �Hardware-based Real-time Workload Forensics,� IEEE Design & Test of Computers (D&T), vol. 37, no. 4, pp. 52-58, 2020 (pdf)
15. M. Zaman, M. Shihab, A. Coskun, Y. Makris, "CAPE: A Cross-Layer Framework for Accurate Microprocessor Power Estimation," Integration: The VLSI Journal (JVLSI), Elsevier, vol. 68, no. 5, pp. 87-98, 2019 (pdf)
16. K. Subramani, A. Antonopoulos, A. Abotabl, A. Nosratinia, Y. Makris, "Demonstrating and Mitigating the Risk of a FEC-based Hardware Trojan in Wireless Networks," IEEE Transactions on Information Forensics and Security (T.IFS), vol. 14, no. 10, pp. 2720-2734, 2019 (pdf)
17. A. Antonopoulos, C. Kapatsori, Y. Makris, "Trusted Analog/Mixed-Signal/RF ICs: A Survey and a Perspective," IEEE Design & Test of Computers (D&T), vol. 34, no. 6, pp. 63-76, 2017 (pdf)
18. A. Ahmadi, H.-G. Stratigopoulos, K. Huang, A. Nahar, B. Orr, M. Pas, J. M. Carulli, Y. Makris, "Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 36, no. 12, pp. 2120-2133, 2017 (pdf)
19. Y. Jin, X. Guo, R. G. Dutta, M. Bidmeshki, Y. Makris, "Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP (Part I: Framework Fundamentals)," IEEE Transactions on Information Forensics and Security (T.IFS), vol. 12, no. 10, pp. 2416-2429, 2017 (pdf)
20. M. Bidmeshki, X. Guo, R. G. Dutta, Y. Jin, Y. Makris, "Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP (Part II: Framework Automation)," IEEE Transactions on Information Forensics and Security (T.IFS), vol. 12, no. 10, pp. 2430-2443, 2017 (pdf)
21. Y. Liu, Y. Jin, A. Nosratinia, Y. Makris, "Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs," IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 25, no. 4, pp. 1506-1519, 2017 (pdf)
22. G. Volanis, A. Antonopoulos, A. Hatzopoulos, Y. Makris, "Toward Silicon-Based Cognitive Neuromorphic ICs - A Survey," IEEE Design & Test of Computers (D&T), vol. 33, no. 3, pp. 91-102, 2016 (pdf)
23. M. Maniatakos, M. Michael, Y. Makris, "Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving," IEEE Transactions on Very Large Scale of Integration Systems (T.VLSI), vol. 23, no. 11, pp. 2447-2460, 2015 (pdf)
24. M. Maniatakos, M. Michael, C. Tirumurti, Y. Makris, "Revisiting Vulnerability Analysis in Modern Microprocessors," IEEE Transactions on Computers (TCOMP), vol. 64, no. 9, pp. 2664-2674, 2015 (pdf)
25. D. Maliuk, Y. Makris, "An Experimentation Platform for On-chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs," IEEE Transactions on Neural Networks and Learning Systems (T.NNLS), vol. 26, no. 8, pp. 1721-1734, 2015 (pdf)
26. K. Huang, N. Korolja, J. M. Carulli Jr., Y. Makris, "Recycled IC Detection based on Statistical Methods," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 34, no. 6, pp. 947-960, 2015 (pdf)
27. K. Huang, N. Kupp, C. Xanthopoulos, J. M. Carulli Jr., Y. Makris, "Low-Cost Analog/RF IC Testing through Combined Intra- and Inter-Die Correlation Models," Special Issue on Speeding up Analog Integration and Test for Mixed-signal SOCs of the IEEE Design & Test of Computers (D&T), vol. 32, no. 1, pp. 53-60, 2015 (pdf)
28. U. Guinn, K. Huang, D. DiMase, J. M. Carulli Jr., M. Tehranipoor, Y. Makris, "Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain," Proceedings of the IEEE (P.IEEE), vol. 102, no. 8, pp. 1207-1228, 2014 (pdf)
29. N. Karimi, M. Maniatakos, C. Tirumurti, Y. Makris, "On the Impact of Performance Faults in Modern Microprocessors,"� Journal of Electronic Testing: Theory & Applications (JETTA), Springer, vol. 29, no. 3, pp. 351-366, 2013 (pdf)
30. M. Maniatakos, P. Kudva, B. Fleischer, Y. Makris, "Low-cost Concurrent Error Detection for Floating Point Unit (FPU) Controllers,"� IEEE Transactions on Computers (TCOMP), vol. 62, no. 7, pp. 1376-1388, 2013 (pdf)
31. M. Maniatakos, C. Tirumurti, Y. Makris, "Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening on Modern Microprocessors,"� IEEE Transactions on Computers (TCOMP), vol. 61, no. 9, pp. 1361-1370, 2012 (pdf)
32. N. Kupp, Y. Makris, "Applying the Model-View-Controller Paradigm to Adaptive Test,"� Special Issue on Yield Learning of the IEEE Design and Test of Computers (D&T), vol. 29, no. 1, pp. 28-35, 2012 (pdf)
33. E. Love, Y. Jin, Y. Makris, "Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition,"� Special Issue on Integrated Circuits and System Security of the IEEE Transactions on Information Forensics and Security (TIFS), vol. 7, no. 1, pp. 25-40, 2012 (pdf)
34. N. Kupp, H. Huang, P. Drineas, Y. Makris, "Improving Analog and RF Device Yield through Performance Calibration,"� IEEE Design and Test of Computers (D&T), vol. 28, no.3, pp. 64-75, 2011 (pdf)
35. N. Karimi, M. Maniatakos, C. Tirumurti, A. Jas, Y. Makris, "A Workload-Cognizant Concurrent Error Detection Method for a Modern Microprocessor Controller,"� Special issue of IEEE Transactions on Computers (TCOMP) on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems, vol. 60, no. 9, pp. 1174-1187, 2011 (pdf)
36. M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, "Instruction-Level Impact Analysis of Low-Level Errors in a Modern Microprocessor Controller,"� Special issue of IEEE Transactions on Computers (TCOMP) on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems, vol. 60, no. 9, pp. 1160-1173, 2011 (pdf)
37. Y. Jin, Y. Makris, "Hardware Trojans in Wireless Cryptographic Integrated Circuits,"� Special issue of IEEE Design & Test of Computers (D&T) on Verifying Physical Trustworthiness of Integrated Circuits and Systems, vol. 27, no. 1, pp. 26-35, 2010 (pdf)
38. H-G. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, "RF Specification Test Compaction using Learning Machines,"� IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 18, no. 6, pp. 1002-1006, 2010 (pdf)
39. N. Kupp, P. Drineas, M. Slamani, Y. Makris, "On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction,"� Journal of Electronic Testing Theory and Applications (JETTA), Springer, vol. 25, no. 6, pp. 309-321, 2009 (pdf)
40. S. Almukhaizim, P. Drineas, Y. Makris, "Parity-Based Concurrent Error Detection with Bounded-Latency in Finite State Machines,"� Kuwait Journal of Science and Engineering (KJSE), vol. 36, no. 2B, pp. 141-162, 2009 (pdf)
41. S. Almukhaizim, F. Shi, E. Love, Y. Makris, "Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits,"� IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 17, no. 7, pp. 869-882, 2009 (pdf)
42. F. Shi, Y. Makris, "Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits,"� IEEE Transactions on Computers (T.COMP), vol. 58, no. 3, pp. 394-408, 2009 (pdf)
43. H-G. D. Stratigopoulos, Y. Makris, "Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing,"� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 27, no. 2, pp. 339-351, 2008 (pdf)
44. S. Almukhaizim, Y. Makris, "A Novel Soft Error Rate (SER) Reduction Methodology through Addition of Gate-Level Functional Redundancy,"� IEEE Transactions on Reliability (T. REL), vol. 57, no. 1, pp. 23-31, 2008 (pdf)
45. S. Almukhaizim, Y. Makris, "Concurrent Error Detection Methods for Asynchronous Burst Mode Machines,"� IEEE Transactions on Computers (T. COMP), vol. 56, no. 6, pp. 785-798, 2007 (pdf)
46. Y. Makris, A. Orailoglu, "On the Identification of Modular Test Requirements for Low-Cost Hierarchical Test Path Construction,"� Integration: The VLSI Journal (JVLSI), Elsevier, vol. 40, no. 3, pp. 315-325, 2007 (pdf)
47. H-G. D. Stratigopoulos, Y. Makris, "An Adaptive Checker for the Fully Differential Analog Code,"� IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6, pp. 1421-1429, 2006 (pdf)
48. S. Almukhaizim, P. Drineas, Y. Makris, "Entropy-Driven Parity Tree Selection for Low-Cost Concurrent Error Detection,"� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 25, no. 8, pp. 1547-1554, 2006 (pdf)
49. H-G. D. Stratigopoulos, Y. Makris, "Concurrent Error Detection in Linear Analog Circuits,"� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 25, no. 5, pp. 878-891, 2006 (pdf)
50. H-G. D. Stratigopoulos, Y. Makris, "Non-Linear Decision Boundaries for Testing Analog Circuits,"� IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD), vol. 24, no. 11, pp. 1760-1773, 2005 (pdf)
51. S. Almukhaizim, P. Drineas, Y. Makris, "Compaction-Based Concurrent Error Detection for Digital Circuits,"� Microelectronics Journal (MJ), Elsevier, vol. 36, no. 9, pp. 856-862, 2005 (pdf)
52. H-G. D. Stratigopoulos, Y. Makris, "An Analog Checker with Input-Relative Tolerance for Duplicate Signals,"� Journal of Electronic Testing: Theory & Applications (JETTA), Kluwer Academic Publishers (now Springer), vol. 20, no. 5, pp. 479-488, 2004 (pdf)
53. Y. Makris, I. Bayraktaroglu, A. Orailoglu, "Enhancing Reliability of RTL Controller-Datapath Circuits via Invariant-Based Concurrent Test,"� IEEE Transactions on Reliability (T. REL), vol. 53, no. 2, pp. 269-278, 2004 (pdf)
54. P. Drineas, Y. Makris, "SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs,"� IEEE Transactions on Instrumentation and Measurement (T. I &M), vol. 52, no. 6, pp. 1729-1737, 2003 (pdf)
55. Y. Makris, J. Collins, A. Orailoglu, "Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface,"� Journal of Electronic Testing: Theory & Applications (JETTA), Kluwer Academic Publishers (now Springer), vol. 18, no. 1, pp. 29-42, 2002 (pdf)
56. Y. Makris, A. Orailoglu, "RTL Test Justification and Propagation Analysis for Modular Designs,"� Journal of Electronic Testing: Theory & Applications (JETTA), Kluwer Academic Publishers (now Springer), vol. 13, no. 2, pp. 105-120, 1999 (pdf)

Conference Papers

1. C. Vasileiou, J. Smith, S. Thiagarajan, M. Nigh, Y. Makris, M. Torlak, �Efficient CNN-Based Super Resolution Algorithms for mmWave Mobile Radar Imaging,� Proceedings of the IEEE International Conference on Image Processing (ICIP), 2022 (to appear)
2. V. Niranjan, D. Neethirajan, A. Nahar, D. Webster, Y. Makris, �Reducing Underkill Using Unsupervised Machine Learning-Based Method in Analog/RF IC Testing,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2022 (pdf)
3. S. Thiagarajan, S. Natarajan, Y. Makris, �A Defect Tolerance Framework for Improving Yield,� Proceedings of the ACM/IEEE Design Automation Conference, pp. 847-852, 2022 (pdf)
4. A. J. Edwards, N. Hassan, D. Bhattacharya, M. Shihab. P. Zhou, X. Hu, J. Atulasimha, Y. Makris, J. Friedman, �Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits,� Proceedings of the IEEE Design, Automation & Test in Europe Conference (DATE), pp. 17-22, 2022 (pdf)
5. D. Neethirajan, V. Niranjan, R. Willis, A. Nahar, D. Webster, Y. Makris, �Machine Learning-Based Overkill Reduction through Inter-Test Correlation,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-7, 2022 (pdf)
6. L. Nahar, J. Rajendran, Y. Makris, C. Sechen, "MTBoM: Metal Trace to Bill of Materials Generation for PCB Reverse Engineering," Proceedings of the IEEE Dallas Circuit and System Conference (DCAS), pp. 1-6, 2022 (pdf)
7. Q. Huang, J. Tian, T. Broadfoot, X. Xu, B. Hu, M. Shihab, A. Jain, V. Salimath, Y. Makris, C. Sechen, "Toward Accurate Timing Analysis for Transistor-Level Programmable Fabrics, Proceedings of the IEEE Dallas Circuit and System Conference (DCAS), pp. 1-6, 2022 (pdf) (Best Paper Award)
8. C. Sathe, Y. Makris, B. Carrion Schaefer, �Investigating the Effect of different eFPGAs fabrics on Logic Locking through HW Redaction,� Proceedings of the IEEE Dallas Circuit and System Conference (DCAS), pp. 1-6, 2022 (pdf)
9. V. Niranjan, D. Neethirajan, A. Nahar, D. Webster, Y. Makris, �Machine-Learning Based Overkill Reduction using Correlation within the Probe Tests,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2021 (pdf)
10. N. Hassan, A. J. Edwards, D. Bhattacharya, M. M. Shihab, V. Venkat, P. Zhou, X. Hu, S. Kundu, A. P. Kuruvila, K. Basu, J. Atulasimha, Y. Makris, J. S. Friedman, �Secure Logic Locking with Strain-Protected Nanomagnet Logic,� Proceedings of the Design Automation Conference (DAC), 2021 (pdf)
11. Z. Wang, M. Shayan, Y. Makris, B. Carrion Schaefer, �Functional Locking through Omission: From HLS to Obfuscated Design,� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 1-6, 2021 (pdf)
12. V. Niranjan, D. Neethirajan, C. Xanthopoulos, E. De La Rosa, C. Alleyne, S. Mier, Y. Makris, �Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-7, 2021 (pdf) (Best Paper Award Candidate)
13. Y. Zhang, Y. Makris, �Hardware-Based Detection of Spectre Attacks: A Machine Learning Approach ,� Proceedings of the EEE Asian Hardware�Oriented Security and Trust Symposium (Asian-HOST), pp. 1-6, 2020 (pdf)
14. S. Thiagarajan, S. Natarajan, Y. Makris, �Defect Tolerance Estimation and Netlist Optimization for Digital Designs,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2020 (pdf)
15. M. Shihab, B. Ramanidharan, G. Rajavendra Reddy, J. Tian, W. Swartz, C. Sechen, Y. Makris, �CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric,� Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2020 (pdf)
16. J. Chen, M. Zaman, Y. Makris, R. D. Blanton, S. Mitra, B. Carrion Schafer, �DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY,� Proceedings of the ACM Design Automation Conference (DAC), 2020 (pdf)
17. M. Shihab, B. Ramanidharan, S. Tellakula, G. Rajavendra Reddy, J. Tian, C. Sechen, Y. Makris, �ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric,� Proceedings of the IEEE VLSI Test Symposium (VTS), 2020 (pdf)
18. S. G. R. Nimmalapudi, G. Volanis, Y. Lu, A. Antonopoulos, A. Marshall, Y. Makris, �Range Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs,� Proceedings of the IEEE Design Automation and Test in Europe (DATE), 2020 (pdf)
19. B. Hu, M. Shihab, Y. Makris, B. C. Schaefer, C. Sechen, �An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGA,� Proceedings of the IEEE Design Automation and Test in Europe (DATE), 2020 (pdf)
20. G. Rajavendra Reddy, Y. Makris, �Design Space Exploration For Hotspot Detection,� Proceedings of the IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 1-5, 2019 (pdf)
21. B. Hu, M. Shihab, Y. Makris, B. C. Schaefer, C. Sechen, �Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage,� Proceedings of the International Conference on Field-Programmable Technology (ICFPT), pp. 291-294, 2019 (pdf)
22. M. Bidmeshki, K. Subramani, Y. Makris, �Revisiting Capacitor-Based Trojan Design and Detection,� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 1-5, 2019 (pdf)
23. G. Rajavendra Reddy, M. Bidmeshki, Y. Makris, �VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration,� Proceedings of the IEEE International Test Conference (ITC), 2019 (pdf)
24. K. Schaub, K. Ikeda, I. Leventhal, Y. Makris, C. Xanthopoulos and D. Neethirajan, �IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning Based Image Completion,� Proceedings of the IEEE International Test Conference (ITC), 2019 (pdf)
25. G. Rajavendra Reddy, Y. Makris, �Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders,� Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp. 1-8, 2019 (pdf)
26. D. Neethirajan, C. Xanthopoulos, S. Boddikurapati, A. Nahar, Y. Makris, �Wafer-Level Adaptive Vmin Calibration Seed Forecasting using Inter-Vmin Correlation,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2019 (pdf)
27. G. Rajavendra Reddy, M. Bidmeshki, Y. Makris, �VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2019 (pdf)
28. A. Antonopoulos, G. Volanis, Y. Lu, Y. Makris �Post-Production Calibration of Analog/RF ICs: Recent Developments and A Fully Integrated Solution,� Proceedings of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 77-80, 2019 (pdf)
29. K. Subramani, G. Volanis, M. Bidmeshki, A. Antonopoulos, Y. Makris, �Trusted and Secure Design of Analog/RF ICs: Recent Developments,� Proceedings of the International On-Line Test Symposium (IOLTS), pp. 125-128, 2019 (pdf)
30. C. Xanthopoulos, Y. Makris, K.-P. Tschernay, A. Neckermann, P. List, P. Sarson, �Automated Die Inking through On-line Machine Learning,� Proceedings of the International On-Line Test Symposium (IOLTS), pp. 27-32, 2019 (pdf)
31. B. Hu, J. Tian, M. Shihab, G. Rajavendra Reddy, W. Swartz, Y. Makris, B. Carrion Schaefer, C. Sechen, �Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA,� Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 171-176, 2019 (pdf)
32. D. Neethirajan, C. Xanthopoulos, K. Subramani, K. Schaub, I. Leventhal, Y. Makris, �Machine Learning-based Noise Classification and Decomposition in RF Transceivers,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2019 (pdf)
33. Y. Zhang, L. Zhou, Y. Makris, �Hardware-based Real-time Workload Forensics via Frame-level TLB Profiling,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2019 (pdf)
34. G. Volanis, Y. Lu, S. Nimmalapudi, A. Antonopoulos, A. Marshall, Y. Makris, �Analog Performance Locking through Neural Network-Based Biasing,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2019 (pdf)
35. C. Xanthopoulos, D. Neethirajan, S. Boddikurapati, A. Nahar, Y. Makris, �Wafer-Level Adaptive Vmin Calibration Seed Forecasting,� Proceedings of the IEEE Design Automation and Test in Europe (DATE), pp. 1673-1678, 2019 (pdf)
36. M. Shihab, J. Tian, G. Rajavendra Reddy, B. Hu, W. Swartz Jr., B. Carrion Schaefer, C. Sechen, Y. Makris, �Design obfuscation with Selective Post-Fabrication Transistor-level Programming,� Proceedings of the IEEE Design Automation and Test in Europe (DATE), pp. 528-533, 2019 (pdf)
37. C. Kapatsori, Y. Liu, A. Antonopoulos, Y. Makris, �Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs,� Proceedings of the IEEE International Test Conference (ITC), pp. 6.3.1-6.3.7, 2018 (pdf)
38. M. Andraud, L. Galindez, Y. Lu, Y. Makris, M. Verhelst, �On the Use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs, Proceedings of the IEEE International Test Conference (ITC), pp. 4.1.1-4.1.10, 2018 (pdf)
39. G. Rajavendra Reddy, J. Wallner, K. Babich, Y. Makris, �Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation,� Proceedings of the ASM International Symposium for Test and Failure Analysis (ISTFA), pp. 1-5, 2018 (pdf)
40. M. Zaman, M. Shihab, A. Coskun, Y. Makris, �Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs,� Proceedings of the International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 229-236, 2018 (pdf)
41. D. Neethirajan, C. Xanthopoulos, S. Boddikurapati, A. Nahar, Y. Makris, �Wafer-Level Adaptive Vmin Seed Forecasting�, Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2018 (pdf)
42. G. Rajavendra Reddy, Y. Makris �Hotspot Detection Through Clustering Based Root Cause Learning�, Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2018 (Top-10 Student Presentations Award) (pdf)
43. G. Rajavendra Reddy, C. Xanthopoulos, Y. Makris, �Enhanced Hotspot Detection Through Synthetic Pattern Generation and Design of Experiments,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2018 (pdf)
44. L. Zhou, Y. Makris, �Hardware-Assisted Rootkit Detection via On-line Statistical Fingerprinting of Process Execution,� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), 2018 (pdf)
45. M. Zaman, A. Sengupta, D. Liu, O. Sinanoglu, Y. Makris, J. Rajendran, �Towards Provably-Secure Performance Locking,� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), 2018 (pdf)
46. K. Subramani, A. Antonopoulos, A. Abotabl, A. Nosratinia, Y. Makris, "ACE: Adaptive Channel Estimation for Detecting Analog/RF Trojans in WLAN Transceivers," Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp. 722-727, 2017 (pdf)
47. C. Xanthopoulos, P. Sarson, H Reiter, Y. Makris, �Automated Die Inking: A Pattern Recognition-Based Approach,� Proceedings of the IEEE International Test Conference (ITC), pp. 12.1.1-12.1.6, 2017 (pdf)
48. G. Rajavendra Reddy, C. Xanthopoulos, Y. Makris, �Enhanced Hotspot Detection Through Synthetic Hotspot Generation and Design of Experiments,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2017 (Best-in-Session Award) (pdf)
49. C. Xanthopoulos, A. Ahmadi, S. Boddikurapati, A. Nahar, B. Orr, Y. Makris, �Wafer-Level Adaptive Trim Seed Forecasting,� Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, 2017 (pdf)
50. A. Antonopoulos, C. Kapatsori, Y. Makris, �Security and Trust in the Analog/Mixed-Signal/RF Domain: A Survey and a Perspective,� Proceedings of the IEEE European Test Symposium (ETS), pp. 1-10, 2017 (pdf)
51. M. Yasin, A. Sengupta, B. Carrion Schaefer, Y. Makris, O. Sinanoglu, J. Rajendran�What to Lock? Functional and Parametric Locking,� Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 351-356, 2017 (pdf)
52. K. Subramani, A. Antonopoulos, A. Abotabl, A. Nosratinia, Y. Makris, �INFECT: INconspicuous FEC-based Trojan: A Hardware Attack on an 802.11a/g Wireless Network,� Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 90-94, 2017 (pdf)
53. Y. Lu, G. Volanis, K. Subramani, A. Antonopoulos, Y. Makris, �Knob Non-Idealities in Learning-Based Post-Production Tuning of Analog/RF ICs: Impact & Remedies,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2017 (pdf)
54. L. Zhou, Y. Makris, �Hardware-based On-line Intrusion Detection via System Call Routine Fingerprinting,� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1546-1551, 2017 (pdf)
55. M. Bidmeshki, A. Antonopoulos, Y. Makris, �Information Flow Tracking in Analog/Mixed-Signal Designs through Proof-Carrying Hardware IP,� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1703-1708, 2017 (pdf)
56. J. Tian, G. Rajavendra Reddy, J. Wang, W. Swartz Jr., Y. Makris, C. Sechen, �A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration,� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1336-1341, 2017 (pdf)
57. L. Zhou, Y. Makris, �Hardware-based Workload Forensics and Malware Detection in Microprocessors,� Proceeding of the iEEE International Workshop on Microprocessor/SoC Test and Verification (MTV), pp. 1-6, 2016 (pdf)
58. A. Ahmadi, M. Bidmeshki, A. Nahar, B. Orr, M. Pas, Y. Makris, �A Machine Learning Approach to Fab-of-Origin Attestation,� Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 92-97, 2016 (pdf)
59. A. Ahmadi, C. Xanthopoulos, A. Nahar, B. Orr, M. Pas, Y. Makris, �Harnessing Process Variations for Optimizing Wafer-Level Probe-Test Flow,� Proceedings of the IEEE International Test Conference (ITC), pp. 5.3.1 � 5.3.8, 2016 (pdf)
60. M. Bidmeshki, G. Rajavendra Reddy, L. Zhou, J. Rajendran, Y. Makris, �Hardware-Based Attacks to Compromise the Cryptographic Security of an Election System,� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 153-156, 2016 (pdf)
61. A. Ahmadi, C. Xanthopoulos, Y. Makris, �Harnessing Process Variation Signature for Dynamic Selection of Probe-Test Flow,� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2016 (pdf)
62. A. Jha, A. Ahmadi, S. Kshattry, T. Cao, K. Liao, G. Yeap, Y. Makris, K. K. O, �-197dBc/Hz FOM 4.3-GHz VCO Using an Addressable Array of Minimum-Sized NMOS Cross-Coupled Transistor Pairs in 65-nm CMOS,� Proceedings of the IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 1-2, 2016 (pdf)
63. A. Ahmadi, A. Nahar, B. Orr, M. Pas, J. Carulli, Y. Makris, �Harnessing Fabrication Process Signature for Predicting Yield Across Designs,� Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 898-901, 2016 (invited) (pdf)
64. L. Zhou, Y. Makris, �Hardware-Based Workload Forensics: Process Reconstruction via TLB Monitoring,� Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST), pp. 167-172, 2016 (pdf)
65. A. Ahmadi, A. Nahar, B. Orr, M. Pas, J. Carulli, Y. Makris, �Wafer-Level Process Variation-Driven Probe-Test Flow Selection for Test Cost Reduction in Analog/RF ICs,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2016 (Best Paper Award Candidate) (pdf)
66. G. Volanis, D. Maliuk, Y. Lu, K. Subramani, A. Antonopoulos, Y. Makris, �On-Die Learning-Based Self-Calibration of Analog/RF ICs,� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6, 2016 (pdf)
67. A. Ahmadi, H. Stratigopoulos, A. Nahar, B. Orr, M. Pas, Y. Makris, "Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 9-14, 2015 (pdf)
68. Y. Lu, K. Subramani, H. Huang, N. Kupp, K. Huang, Y. Makris, "A Comparative Study of One-Shot Statistical Calibration Methods for Analog / RF ICs," Proceedings of the IEEE International Test Conference (ITC), pp. 4.1.1-4.1.8, 2015 (pdf)
69. Y. Liu, G. Volanis, K. Huang, Y. Makris, "Concurrent Hardware Trojan Detection in Wireless Cryptographic ICs," Proceedings of the IEEE International Test Conference (ITC), pp. 21.3.1-21.3.10, 2015 (pdf)
70. M. Zaman, A. Ahmadi, Y. Makris, �Reliability Enhancement of Multi-core Processors Using Machine-Learning Techniques," Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), pp. 1-4, 2015 (pdf)
71. Y. Lu, K. Subramani, H. Huang, N. Kupp, Y. Makris, "Silicon Demonstration of Statistical Post-Production Tuning," Proceedings of the International Symposium on VLSI (ISVLSI), pp.628-633, 2015 (invited) (pdf)
72. M. Zaman, A. Ahmadi, Y. Makris, "Workload Characterization and Prediction: A Pathway to Reliable Multi-core Systems," Proceedings of the International On-Line Test Symposium (IOLTS), pp. 116-121, 2015 (pdf)
73. M. Bidmeshki, Y. Makris, "Toward Automatic Proof Generation for Information Flow Policies in Third-Party Hardware IP," Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST), pp. 163-168, 2015 (pdf)
74. M. Bidmeshki, Y. Makris, "VeriCoq: a Verilog-to-Coq Converter for Proof-Carrying Hardware Automation," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 29-32, 2015 (invited) (pdf)
75. A. Ahmadi, K. Huang, A. Nahar, B. Orr, M. Pas, J. Carulli, Y. Makris, "Yield Prognosis for Fab-to-Fab Product Migration," Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 1-6 2015 (pdf) (Best Paper Award)
76. A. Ahmadi, K. Huang, S. Natarajan, J. Carulli, Y. Makris, "Spatiotemporal Wafer-level Correlation Modeling with Progressive Sampling: A Pathway to HVM Yield Estimation," Proceedings of the IEEE International Test Conference (ITC), pp. 18.1.1-18.1.9, 2014 (pdf)
77. C. Xanthopoulos, K. Huang, A. Poonawala, A. Nahar, B. Orr, J. Carulli, Y. Makris, "IC Laser Trimming Speed-Up through Wafer-level Spatial Correlation Modeling," Proceedings of the IEEE International Test Conference (ITC), pp. 19.2.1-19.2.8, 2014 (pdf)
78. D. Maliuk, Y. Makris, "On-chip intelligence: A pathway to self-testable, tunable, and trusted analog/RF ICs," Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1077-1080, 2014 (pdf)
79. Y. Liu, K. Huang, Y. Makris, "Hardware Trojan detection through golden chip-free statistical side-channel fingerprinting," Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2014 (pdf)
80. D. Maliuk, Y. Makris, "An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions," Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1-6, 2014 (pdf)
81. Y. Jin, Y. Makris, "A Proof-Carrying Based Framework for Trusted Microprocessor IP," Proceedings of the ACM/IEEE Design Automation Conference (ICCAD), pp. 824-829, 2013 (pdf)
82. Y. Liu, Y. Jin, Y. Makris, "Hardware Trojans in Wireless Cryptographic ICs: Silicon Demonstration & Detection Method Evaluation,"� Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 399-404, 2013 (pdf)
83. K. Huang, N. Kupp, J. Carulli, Y. Makris, "Process Monitoring through Wafer-level Spatial Variation Decomposition,"� Proceedings of the IEEE International Test Conference (ITC), S5.3.1-S5.3.10, 2013 (pdf)
84. K. Huang, J. Carulli, Y. Makris, "Counterfeit Electronics: A Rising Threat in the Semiconductor Manufacturing Industry,"� Proceedings of the IEEE International Test Conference (ITC), L3.4.1-L3.4.4, 2013 (pdf)
85. Y. Jin, D. Maliuk, Y. Makris, "A Post-Deployment IC Trust Evaluation Architecture,"� Proceedings of the IEEE On-Line Test Symposium (IOLTS), pp. 224-225, 2013 (pdf)
86. M. Maniatakos, M. Michael, Y. Makris, "Challenges and Benefits of Multiple Bit Upset (MBU) Vulnerability Analysis in Modern Microprocessors,"� Proceedings of the IEEE On-Line Test Symposium (IOLTS), pp. 49-54, 2013 (pdf)
87. Y. Jin, B. Yang, Y. Makris, "Cycle Accurate Information Assurance by Proof Carrying-Based Signal Sensitivity Tracing,"� Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 99-106, 2013 (pdf)
88. O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, Y. Makris, "Reconciling the IC Test and Security Dichotomy,"� Proceedings of the IEEE European Test Symposium (ETS), pp. 176-181, 2013 (pdf)
89. K. Huang, N. Kupp, J. Carulli, Y. Makris, "On Combining Alternate Test with Spatial Correlation Modeling in Analog/RF ICs,"� Proceedings of the IEEE European Test Symposium (ETS), pp. 64-69, 2013 (pdf)
90. K. Huang, N. Kupp, J. Carulli, Y. Makris, "Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 553-558, 2013 (Best Paper Award) (pdf)
91. M. Maniatakos, M. Michael, Y. Makris, "AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1480-1485, 2013 (pdf)
92. N. Kupp, Y. Makris, "Integrated Optimization of Semiconductor Manufacturing: A Machine Learning Approach,"� Proceedings of the IEEE International Test Conference (ITC), pp. PTF.1.1-PTF.1.10, 2012 (pdf)
93. N. Kupp, K. Huang, J. Carulli, Y. Makris, "Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models,"� Proceedings of the IEEE International Test Conference (ITC), pp. 5.1.1-5.1.8, 2012 (pdf)
94. M. Maniatakos, M. Michael, Y. Makris, "Vulnerability-Based Interleaving for Multi-Bit Upset (MBU) Protection in Modern Microprocessors,"� Proceedings of the IEEE International Test Conference (ITC), pp. 19.2.1-19.2.8, 2012 (pdf)
95. N. Kupp, K. Huang, J. Carulli, Y. Makris, "Spatial Correlation Modeling For Probe Test Cost Reduction in RF Devices,"� Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp. 23-29, 2012 (pdf)
96. K. Huang, J. Carulli, Y. Makris, "Parametric Counterfeit IC Detection via Support Vector Machines,"� Proceedings of the IEEE Defect and Fault Tolerance Symposium (DFTS), pp. 7-12, 2012 (pdf)
97. Y. Jin, M. Maniatakos, Y. Makris, "Exposing Vulnerabilities of Untrusted Computing Platforms,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 131-134, 2012 (pdf)
98. D. Maliuk, Y. Makris, "A Reconfigurable Dual-Mode Weight Storage Analog Neural Network Experimentation Platform,"� Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2889-2892, 2012 (pdf)
99. Y. Jin, Y. Makris, "Proof Carrying-Based Information Flow Tracking for Data Secrecy Protection and Hardware Trust,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 252-257, 2012 (pdf)
100. D. Maliuk, N. Kupp, Y. Makris, "Towards a Fully Stand-Alone Analog/RF BIST: A Cost-Effective Implementation of a Neural Classifier,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 62-67, 2012 (pdf)
101. Y. Jin, D. Maliuk, Y. Makris, "Post-Deployment Trust Evaluation in Wireless Cryptographic ICs,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 965-970, 2012 (pdf)
102. Y. Jin, Y. Makris, "PSCML: Pseudo-Static Current Mode Logic,"� Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 41-44, 2011 (pdf)
103. N. Kupp, H.-G. Stratigopoulos, P. Drineas, Y. Makris, "On Proving the Performance of Alternative RF Tests,"� Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp.762-767, 2011 (pdf)
104. Y. Jin, Y. Makris, "Is Single-Scheme Trojan Prevention Sufficient?,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 305-308, 2011 (pdf)
105. N. Kupp, H. Stratigopoulos, P. Drineas, Y. Makris, "Feature Selection Methods For Analog and RF Test: A Case Study"� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), 2011 (Best-in-Session Award) (pdf)
106. E. Love, Y. Jin, Y. Makris, "Enhancing Security via Provably Trustworthy Hardware Intellectual Property,"� Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST), pp. 12-17, 2011 (pdf)
107. M. Maniatakos, C. Tirumurti, A. Jas, Y. Makris, "AVF Analysis Acceleration via Hierarchical SFI,"� Proceedings of the IEEE European Test Symposium (ETS), pp. 87-92, 2011 (pdf)
108. N. Kupp, H. Stratigopoulos, P. Drineas, Y. Makris, "PPM-Accuracy Error Estimates for Low-Cost Analog Test: A Case Study,"� Proceedings of the IEEE International Mixed Signals, Sensors, and Systems Workshop (IMS3TW), 2011 (Best Student Paper Award) (pdf)
109. M. Maniatakos, P. Kudva, B. Fleischer, Y. Makris, "Exponent Monitoring for Low-Cost Concurrent Error Detection in FPU Control Logic,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 235-240, 2011 (pdf)
110. N. Kupp, M. Slamani, Y. Makris, "Correlating Inline Data with Final Test Outcomes in Analog/RF Devices,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 812-817, 2011 (pdf)
111. Y. Jin, N. Kupp, Y. Makris, "DFTT: Design for Trojan Test,"� Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS), pp. 1175-1178, 2010 (pdf)
112. D. Maliuk, H. Stratigopoulos, H. Huang, Y. Makris, "Analog Neural Network Design for RF Built-In Self-Test,"� Proceedings of the IEEE International Test Conference (ITC), pp. 23.2.1-23.2.10, 2010 (pdf)
113. N. Kupp, H. Huang, P. Drineas, Y. Makris, "Post-Production Performance Calibration in Analog/RF Devices,"� Proceedings of the IEEE International Test Conference (ITC), 8.3.1-8.3.10, 2010 (pdf)
114. D. Maliuk, H. Stratigopoulos, Y. Makris, "An Analog VLSI Implementation of a Multilayer Perceptron and its Application Towards Built-In Self-Test in Analog Circuits,"� Proceedings of the IEEE International On-Line Test Symposium (IOLTS), pp. 71-76, 2010 (pdf)
115. M. Maniatakos, Y. Makris, "Workload-Driven Selective Hardening of Control State Elements in Modern Microprocessors,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 159-164, 2010 (pdf)
116. N. Karimi, M. Maniatakos, C. Tirumurti, A. Jas, Y. Makris, "Impact Analysis of Performance Faults in Modern Microprocessors,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 91-96, 2009 (pdf)
117. N. Kupp, H. Huang, Y. Makris, "Post-Production Tuning in Analog and RF Devices,"� Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON), 2009 (pdf)
118. Y. Jin, N. Kupp, Y. Makris, "Experiences in Hardware Trojan Design and Implementation,"� Proceedings of the IEEE International Workshop on Hardware Oriented Security and Trust (HOST), pp 65-70, 2009 (pdf)
119. M. Maniatakos, N. Karimi, C. Tirumurti, A. Jas, Y. Makris, "Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 9-14, 2009 (pdf)
120. H-G. Stratigopoulos, S. Mir, Y. Makris, "Enrichment of Limited Training Sets in Machine Learning-Based Analog/RF Test,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1124-1129, 2009 (pdf)
121. N. Karimi, M. Maniatakos, A. Jas, Y. Makris, "On the Correlation between Controller Faults and Instruction-Level Errors in a Modern Microprocessor,"� Proceedings of the IEEE International Test Conference (ITC), pp. 24.1.1-24.1.10, 2008 (pdf)
122. M. Maniatakos, N. Karimi, Y. Makris, A. Jas, C. Tirumurti, "Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller,"� Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 454-462, 2008 (pdf)
123. S. Almukhaizim, Y. Makris, Y.-S. Yang, A. Veneris, "On the Minimization of Potential Transient Errors and SER in Logic Circuits using SPFD,"� Proceedings of the IEEE International On-Line Testing Symposium (IOLTS), pp 123-128, 2008 (pdf)
124. Y. Jin, Y. Makris, "Hardware Trojan Detection using Path Delay Fingerprint,"� Proceedings of the IEEE International Workshop on Hardware Oriented Security and Trust (HOST), pp. 54-60, 2008 (pdf)
125. N. Kupp, P. Drineas, M. Slamani, Y. Makris, "Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction,"� Proceedings of the IEEE European Test Symposium (ETS), pp 35-41, 2008 (pdf)
126. J. Dardig, H-G. Stratigopoulos, E. Stern, M. Reed, Y. Makris, "A Statistical Approach to Characterizing and Testing Functionalized Nanowires,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 267-274, 2008 (pdf)
127. S. Almukhaizim, F. Shi, Y. Makris, "Coping with Soft Errors in Asynchronous Burst-Mode Machines,"� Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 151-160, 2008 (pdf)
128. H-G. D. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, "Non-RF to RF Test Correlation Using Learning Machines: A Case Study,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 9-14, 2007 (pdf)
129. F. Shi, Y. Makris, "Testing Delay Faults in Asynchronous Handshake Circuits,"� Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp. 193-197, 2006 (pdf)
130. S. Almukhaizim, Y. Makris, Y.-S. Yang, A. Veneris, "Seamless Integration of SER in Rewiring-Based Design Space Exploration,"� Proceedings of the IEEE International Test Conference (ITC), pp. 29.3.1-29.3.9, 2006 (pdf)
131. H-G. D. Stratigopoulos, Y. Makris, "Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 406-411, 2006 (pdf)
132. F. Shi, Y. Makris, "A Transistor-Level Test Strategy for C2MOS MOUSETRAP Asynchronous Pipelines,"� Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 57-66, 2006 (pdf)
133. G. Gill, A. Agiwal, M. Singh, F. Shi, Y. Makris, "Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines,"� Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 46-56, 2006 (pdf)
134. S. Almukhaizim, Y. Makris, "Berger-Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 71-72, 2006 (pdf)
135. F. Shi, Y. Makris, S. M. Nowick, M. Singh, "Test Generation for Ultra-High-Speed Asynchronous Pipelines,"� Proceedings of the IEEE International Test Conference (ITC), pp. 39.1.1-39.1.10, 2005 (pdf)
136. H-G. D. Stratigopoulos, Y. Makris, "Constructive Derivation of Analog Specification Test Criteria,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 395-400, 2005 (pdf)
137. H-G. D. Stratigopoulos, Y. Makris, "Generating Decision Regions in Analog Measurement Spaces,"� Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 88-91, 2005 (pdf)
138. S. Almukhaizim, Y. Makris, "Concurrent Error Detection in Asynchronous Burst-Mode Controllers,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1272-1277, 2005 (pdf)
139. F. Shi, Y. Makris, "SPIN-PAC: Test Compaction for Speed-Independent Circuits,"� Proceedings of the IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp. 91-94, 2005 (pdf)
140. F. Shi, Y. Makris, "SPIN-TEST: Automatic Test Pattern Generation for Speed-Independent Circuits,"� Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), pp. 903-908, 2004 (pdf)
141. F. Shi, Y. Makris, "SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits,"� Proceedings of the IEEE International Test Conference (ITC), pp. 597-606, 2004 (pdf)
142. F. Shi, S. Almukhaizim, P. C. Lin, Y. Makris, "Compiler-Based Frame Formation for Static Optimization,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 466-471, 2004 (pdf)
143. F. Shi, Y. Makris, "Fault Simulation and Random Test Generation for Speed Independent Circuits,"� Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 127-130, 2004 (pdf)
144. S. Almukhaizim, P. Drineas, Y. Makris, "Cost-Driven Selection of Parity Trees,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 319-324, 2004 (pdf)
145. S. Almukhaizim, P. Drineas, Y. Makris, "Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction,"� Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 459-464, 2004 (pdf)
146. S. Almukhaizim, P. Drineas, Y. Makris, "On Concurrent Error Detection with Bounded Latency in FSMs,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 596-601, 2004 (pdf)
147. K. Rokas, Y. Makris, D. Gizopoulos, "Low-Cost Convolutional Code Based Concurrent Error Detection in FSMs,"� Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 563-570, 2003 (pdf)
148. S. Almukhaizim, Y. Makris, "Fault Tolerant Design of Combinational and Sequential Logic based on a Parity Check Code,"� Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 344-351, 2003 (pdf)
149. S. Almukhaizim, T. Verdel, Y. Makris, "Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 194-197, 2003 (pdf)
150. P. Drineas, Y. Makris, "Independent Test Sequence Compaction through Integer Programming,"� Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 380-386, 2003 (pdf)
151. H-G. D. Stratigopoulos, Y. Makris, "Concurrent Error Detection in Linear Analog Circuits Using State Estimation,"� Proceedings of the IEEE International Test Conference (ITC), pp. 1164-1173, 2003 (pdf)
152. H-G. D. Stratigopoulos, Y. Makris, "An Analog Checker with Input-Relative Tolerance for Duplicate Signals,"� Proceedings of the IEEE On-Line Testing Symposium (IOLTS), pp. 54-58, 2003 (pdf)
153. S. Almukhaizim, P. Drineas, Y. Makris, "On Compaction-Based Concurrent Error Detection,"� Proceedings of the IEEE On-Line Testing Symposium (IOLTS), pp. 157, 2003 (pdf)
154. H-G. D. Stratigopoulos, Y. Makris, "An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 209-214, 2003 (pdf)
155. P. Drineas, Y. Makris, "Concurrent Fault Detection in Random Combinational Logic,"� Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 425-430, 2003 (pdf)
156. P. Drineas, Y. Makris, "Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 1164-1165, 2003 (pdf)
157. P. Drineas, Y. Makris, "SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs,"� Proceedings of the IEEE International Conference on VLSI Design (VLSI), pp. 167-173, 2003 (pdf)
158. P. Drineas, Y. Makris, "Non-Intrusive Design of Concurrently Self-Testable FSMs,"� Proceedings of the IEEE Asian Test Symposium (ATS), pp. 33-38, 2002 (pdf)
159. Y. Makris, A. Orailoglu, "Test Requirement Analysis for Low Cost Hierarchical Test Path Construction,"� Proceedings of the IEEE Asian Test Symposium (ATS), pp.134-139, 2002 (pdf)
160. T. Verdel, Y. Makris, "Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies,"� Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 345-353, 2002 (pdf)
161. Y. Makris, V. Patel, A. Orailoglu, "Efficient Transparency Extraction and Utilization in Hierarchical Test,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 246-251, 2001 (pdf)
162. Y. Makris, J. Collins, A. Orailoglu, "Fast Hierarchical Test Path Construction for Controller-Datapath Circuits without DFT,"� Proceedings of the IEEE Asian Test Symposium (ATS), pp. 185-190, 2000 (pdf)
163. Y. Makris, J. Collins, A. Orailoglu, "How to Avoid Random Walks in Hierarchical Test Path Identification,"� Formal Proceedings of the IEEE European Test Workshop (ETW), pp. 163-168, 2000 (pdf)
164. Y. Makris, A. Orailoglu, P. Vishakantaiah, "Modular Test Generation and Concurrent Transparency-Based Test Translation Using Gate-Level ATPG,"� Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 75-78, 2000 (pdf)
165. Y. Makris, J. Collins, A. Orailoglu, P. Vishakantaiah, "Transparency-Based Hierarchical Test Generation for Modular RTL Designs,"� Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS), pp. II 689-692, 2000 (pdf)
166. Y. Makris, I. Bayraktaroglu, A. Orailoglu, "Invariance-Based On-Line Test for RTL Controller-Datapath Circuits,"� Proceedings of the IEEE VLSI Test Symposium (VTS), pp. 459-464, 2000 (pdf)
167. Y. Makris, A. Orailoglu, "A Module Diagnosis and Design-for-Debug Methodology based on Hierarchical Test Paths,"� Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 339-347, 1999 (pdf)
168. Y. Makris, A. Orailoglu, "Property-Based Testability Analysis for Hierarchical RTL Designs,"� Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS), pp. 1089-1092, 1999 (pdf)
169. Y. Makris, J. Collins, A. Orailoglu, P. Vishakantaiah, "TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and Hierarchical Test Generation,"� Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 159-162, 1999 (pdf)
170. Y. Makris, A. Orailoglu, "Channel-Based Behavioral Test Synthesis for Improved Module Reachability,"� Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE), pp. 283-288, 1999 (pdf)
171. Y. Makris, A. Orailoglu, "DFT Guidance Through RTL Test Justification and Propagation Analysis,"� Proceedings of the IEEE International Test Conference (ITC), pp. 668-677, 1998 (pdf)

Papers in Workshops with Informal Proceedings

1. D. Maliuk, Y. Makris, "Analog Implementation of Ontogenic Neural Networks for RF Built-In Self-Test,"� Presented at the IEEE Test and Validation of High-Speed Analog Circuits, Anaheim, CA, USA, Sep '13 (pdf)
2. S. Almukhaizim, P. Drineas, Y. Makris, "Roving Concurrent Error Detection for Logic Circuits,"� Presented at the IEEE North Atlantic Test Workshop, Essex Junction, VT, USA, May '04 (pdf)
3. S. Almukhaizim, Y. Makris, "Fault Tolerant Design of Random Logic based on a Parity Check Code,"� Presented at the IEEE European Test Workshop, Maastricht, Netherlands, May '03 (pdf)
4. P. Drineas, Y. Makris, "On the Compaction of Independent Test Sequences for Sequential Circuits,"� Presented at the IEEE European Test Workshop, Maastricht, Netherlands, May '03 (pdf)
5. Y. Makris, A. Orailoglu, "Reducing Hierarchical Test Path Cost via Modular Test Requirement Analysis,"� Presented at the IEEE European Test Workshop, Corfu, Greece, May '02 (pdf)
6. P. Drineas, Y. Makris, "Non-Intrusive Design of Concurrently Self-Testable FSMs,"� Presented at the IEEE North Atlantic Test Workshop, Montauk, NY, USA, May '02 (pdf)
7. Y. Makris, A. Orailoglu, "Test Requirement Analysis for Low Cost Hierarchical Test Path Construction,"� Presented at the IEEE International Workshop of RTL Test Generation, Nara, Japan, Nov '01 (pdf)
8. Y. Makris, J. Collins, A. Orailoglu, "How to Avoid Random Walks in Hierarchical Test Path Identification,"� Presented at the IEEE European Test Workshop, Cascais, Portugal, May '00 (pdf)
9. Y. Makris, A. Orailoglu, "Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test,"� Presented at the IEEE Latin American Test Workshop, Rio de Janeiro, Brazil, Feb '00 (pdf)
10. Y. Makris, A. Orailoglu, "Property-Based RTL Test Justification and Propagation Analysis,"� Presented at the IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, Mar '98 (pdf)

Note: Copyright of these papers is held by the respective publishing organizations.

� 2001-2022 Yiorgos Makris