Book
B. Staszewski and P. T. Balsara: "AllDigital Frequency Synthesizer in
DeepSubmicron CMOS," WileyInterscience, John Wiley & Sons, Hoboken, New
Jersey, Sept. 2006. ISBN 0471772550.
Selected Journal and Conference Publications
D. Patil, J. Miller, B. Fahimi, J. M. Miller, B. Fahimi, P. T. Balsara, and V.
Galigekere: "A Coil Detection System for Dynamic Wireless Charging of Electric
Vehicle, " to appear in IEEE Transactions on Transportation Electrification.
P. C. Buck, B. Fahimi, and P. T. Balsara: "A Phase Current Peak Prediction Technique to
Increase the Output Power of Switched Reluctance Generators for Wind Turbines,"
Proceedings
of the
IEEE Energy Conversion Congress and Expo (ECCE 2019), Baltimore,
MD, 2019, pp. 52445250.
S. Arora, P.T. Balsara, and D. K. Bhatia: "InputOutput
Linearization of a Boost Converter with Constant Power Load," IEEE
Transactions on Power Electronics, Vol. 34, No. 1, January 2019, pp.
815825.
L. Maharjan, E. Bostanci, S. Wang, E. Cosoroaba, W. Cai, F. Yi, P.
Shamsi, W. Wang, L. Gu, M. Luo, N. Rahman, M. McDonough, C. Lin, J. Hearron, C.
Narvaez, M. Wu, A. Isfahani, Y. Li, G. Rao, M. Moallem, P.T. Balsara, and B.
Fahimi: "Comprehensive Report on Design and Development of a 100kW DSSRM," IEEE
Transactions on Transportation Electrification, Vol. 4, No. 4, December 2018,
pp. 835856.
S. Arora, D. K. Bhatia, P.T. Balsara, and P. Buck: "A Novel
Digital Architecture for Gain and Phase Measurements in a PWM Controller,"
Proceedings of the
IEEE Dallas Circuits and Systems Conference (DCAS'18), Richardson,
Texas. Nov. 12, 2018, pp. 14.
D. Patil, B. Fahimi, J. M. Miller, M. K. McDonough, and P. T. Balsara: "Wireless
Power Transfer for Vehicular Application: Overview and Challenges," IEEE
Transactions on Transportation Electrification, Vol. 4, No. 1, March 2018,
pp. 337.
V. Paduvalli, R. Taylor, L.R. Hunt, and P. T. Balsara: "Mitigation of Positive
Zero Effect on NonMinimum Phase Boost DCDC Converters," IEEE Transactions
on Industrial Electronics, Vol. 65, No. 5, May 2018, pp. 41254134.
A. A. Thulasi, D.K. Bhatia, P.T. Balsara, and S. Prasad: "Portable
Impedance Measurement Device for Sweat Based Glucose Detection," Proceedings
of the International Conference on Wearable and Implantable
Body Sensor Networks (BSN 2017), Eindhoven, The Netherlands, May
912, 2017.
S. R. Srinivasan and P.T. Balsara: "A Hybrid DAC Switching
Technique for SAR ADCs," Analog Integrated Circuits and Signal Processing, Vol.
92, No. 2, August 2017, pp. 179187.
I. Bashir, B. Staszewski, and P. T. Balsara, "Numerical Model of an Injection
Locked Wideband Frequency Modulator for Polar Transmitters,"
IEEE Transactions on Microwave Theory and Techniques
Vol. 65, No. 5, May 2017, pp. 1914192.
V. Paduvalli, R. Taylor, and P. T. Balsara: "Analysis of Zeros in Boost DCDC
Converter: State Diagram Approach," IEEE Transactions on Circuits and
Systems II, Vol. 64, No. 5, May 2017, pp. 550554.
E. Atalla, F. Zhang, P. T. Balsara, A. Bellaouar, S. Ba, and K. Kiasaleh:
"TimeDomain Analysis of Passive Mixer Impedance: A SwitchedCapacitor
Approach," IEEE Transactions on Circuits and Systems  I, Vol.
64, No. 2, 2017, pp. 347359.
S. Arora, P.T. Balsara, and D. K. Bhatia: "Effect of Sampling Time
and Sampling Instant on the Frequency Response of a Boost Converter," Proceedings
of the 42^{nd} IEEE Industrial Electronics Conference (IECON2016),
Florence, Italy, October 2427, 2016. Student Forum Best Paper and
Presentation Award
I. Bashir, B. Staszewski, O. Eliezer, and P. T. Balsara, "A Wideband DigitaltoFrequency Converter with
BIST Mechanism for SelfInterference Mitigation," Journal of Electronic
Testing, Theory and Applications (Springer), Vol. 32, No. 4, 2016,
pp. 437445.
V. Paduvalli, R. Taylor, L.R. Hunt, and P. T. Balsara: "Input Output Linearization
with NonMinimum Phase Boost DCDC Converters," IEICE Nonlinear Theory and
Its Applications (NOLTA) Journal, Vol. 7, No. 3, July 2016,
pp. 419429.
I. Bashir, B. Staszewski, and P. T. Balsara, "A Digitally Controlled Injection
Locked Oscillator with Fine Frequency Resolution,"
IEEE Journal on SolidState Circuits,
vol. 51, no. 6, June 2016, pp. 13471360.
S. K. Manohar and P.T. Balsara: "High Efficiency DCM Buck
Converter with Dynamic Logic Based Adaptive SwitchTime Control," Analog
Integrated Circuits and Signal Processing
84, 3, September 2015, pp. 455469.
S. K. Manohar, L.R. Hunt, P.T. Balsara, D.K. Bhatia, V.V.
Paduvalli: "Minimum Phase Wide Output Range Digitally Controlled SIDO Boost
Converter," IEEE Transactions on Circuits and Systems  I, vol. 62, no.
9, September 2015, pp. 23512360.
S. Modi, P. T. Balsara, and O. Eliezer: "Envelope Tracking using Transient
Waveform Shaping Switching Supply Modulation," International Journal of
Circuit Theory and Applications, vol. 43, no. 5, May 2015, pp. 656674.
S. Arora, P.T. Balsara, D. K. Bhatia, R. J. Taylor, and L. R.
Hunt: "Gain and Phase (GAP) Measurement Device," Proceedings of the 30^{th}
Annual IEEE Applied Power Electronics Conference and Exposition (APEC2015),
Charlotte, NC.
R. Venkatasubramanian, S. K. Manohar and P. T. Balsara: "Heterogeneous NEMSCMOS
DCM Buck Regulator for Improved Area and Enhanced Power Efficiency," IEEE Transactions on Nanotechnology, vol. 14, no.
1, January 2015, pp.140151.
A. Awasthi, R. Guttal, N. AlDhahir and P. T. Balsara: "Complex QR Decomposition
using Fast Plane Rotations for MIMO Applications," IEEE
Communications Letters, vol. 18, no. 10, October 2014, pp. 17431746.
S. R. Srinivasan and P.T. Balsara: "Energyefficient subDAC
merging scheme for variable resolution SAR ADC," IET Electronics Letters, vol.
50, no. 20, September 2014, pp. 14211423.
S. Modi, N. Yanduru, and P.T. Balsara: "Efficiency Improvement of Doherty Power
Amplifier using Supply Switching and Gate Bias Modulation," 15^{th}
Annual IEEE Wireless and Microwave Technology Conference (WAMICON2014),
Cocoa Beach, FL, April 1315, 2014.
E. Atalla, F. Zhang, A. Bellaouar, and P. T. Balsara: "Estimation of Passive Mixer
Output Bandwidth Using SwitchedCapacitor Techniques," 2013 IEEE
Custom Integrated Circuits Conference (CICC), Sept. 2225, 2013, pp.
14.
S. K. Manohar and P.T. Balsara: "94.6% Peak Efficiency DCM Buck Converter with
Fast Adaptive DeadTime Control," 39^{th}
European SolidState Circuits Conference (ESSCIRC), Bucharest,
Romania, Sept 1620, 2013, pp. 153156.
E. Atalla, A. Bellaouar, and P. T. Balsara: "IIP2 Requirements in 4G LTE Handset
Receivers," 2013 IEEE Midwest Circuits and Systems Symposium (MWCAS),
Aug. 47, 2013, pp. 11321135
R. Venkatasubramanian, S. K. Manohar and P. T. Balsara: "NEM Relay Based
Sequential Logic Circuits for Low Power Design," IEEE
Transactions on Nanotechnology, vol. 12, no. 3, May 2013, pp.
386398.
I. Syllaios and P. T. Balsara: "Linear TimeVariant Modeling and Analysis of
AllDigital PhaseLocked Loops," IEEE Transactions on Circuits and
SystemsI, vol. 59, no. 11, November 2012, pp. 24952506.
S. Modi and P.T. Balsara: "Reduced Bandwidth Class H Supply Modulation for
Wideband RF Power Amplifiers " Proceedings of the 13^{th}
Annual IEEE Wireless and Microwave Technology Conference (WAMICON2012),
Cocoa Beach, FL, April 1617, 2012, pp. 17.
J. Mehta, R. B. Staszewski, G. Feygin, O. Eliezer, M. Frechette, and P.T. Balsara: "Mismatch
Considerations in an RFDAC Design for a Digital Polar EDGE Transmitter," Proceedings of
IEEE International Symposium on RadioFrequency Integration Technology (RFIT2011),
Beijing, China. Nov. 30  Dec. 2, 2011, pp. 169172.
Venkatasubramanian, S. K. Manohar and P. T. Balsara: "Improving
Performance of NEM Relay Logic Circuits using Integrated ChargeBoosting
FlipFlop," Proceedings of the IEEE/ACM International Symposium on
Nanoscale Architectures (NANOARCH), 2011.
I. Syllaios and P.T. Balsara: "MultiClock Domain
Analysis and Modeling of AllDigital Frequency Synthesizers," Proceedings of
the IEEE International Symposium on Circuits and Systems (ISCAS),
Rio de Janeiro, Brazil, May 1518, 2011, pp. 153156.
I. Bashir, R. B. Staszewski, O. Eliezer, B. Banerjee and P. T. Balsara: "A Novel
Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter," IEEE
Journal on SolidState Circuits, vol. 46, no. 2, February 2011, pp. 403415
V.K.K. Srinivasan, C. K. Singh and P. T. Balsara: "A Generic Scalable Architecture for
MinSum/OffsetMinSum Unit for Irregular/Regular LDPC Decoder," IEEE
Transactions on VLSI, vol. 18, No. 9, September 2010, pp. 113721376.
S. Modi, S. Askari, S. K. Manohar, N. Yanduru, P.T. Balsara and M. Nourani: "Automated GmC
Filter Design: A Case Study in Accelerated Reuse of Analog Circuit Design," Proceedings of
the 9^{th} IEEE Dallas Circuits and Systems Workshop (DCAS
'0), Richardson, Texas. Oct. 1718, 2010.
I. Syllaios, P. T. Balsara and R. B. Staszewski: "Recombination of Envelope and
Phase Paths in Wideband Polar Transmitters," IEEE Transactions on
Circuits and SystemsI, vol. 57, No. 8, August 2010, pp. 18911904.
J. Mehta, V. Zoicas, O. E. Eliezer, R. B. Staszewski, S. Rezeq, M. Entezari and
P.T. Balsara: "An Efficient Linearization Scheme for a Digital Polar Edge
Transmitter," IEEE Transactions on Circuits and SystemsII, vol.
57, No. 3, March 2010, pp. 193197.
V. Parikh, P. T. Balsara and O. E. Eliezer: "All Digital Quadrature Modulator for
Wideband Wireless Transmitters," IEEE Transactions on Circuits and
SystemsI, vol. 56, No. 11, November 2009, pp. 24872497.
O. Eliezer, B. Staszewski, S. Bhatara, I. Bashir, and P. T. Balsara: "A Phase
Domain Approach for Mitigation of SelfInterference in Wireless Transceivers," IEEE
Journal on SolidState Circuits, vol. 44, No. 5, May 2009, pp. 14361453.
I. Elahi, K. Muhammad, and P. T. Balsara:
"Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation," IEEE
Transactions on Circuits and SystemII, vol. 56, No. 1, January 2009, pp.
8690.
S. Modi, S. Kanigere, O. Eliezer and P. T. Balsara: "Limited Bandwidth Envelope
Follower for Improving Efficiency of Broadband Linear Power Amplifier," Proceeding
of the 7^{th} IEEE Dallas Circuits and Systems Workshop (DCAS'08), Richardson, Texas. Oct. 1920, 2008, pp. 6669
I. Syllaios, P. T. Balsara and R. B. Staszewski: "TimeDomain Modeling of a
PhaseDomain AllDigital PLL," IEEE Transactions on Circuits and
SystemsII, vol. 5, No. 6, June 2008, pp. 601605.
V. Parikh, P. T. Balsara and O. Eliezer: "A Fully Digital Transmitter Architecture for Wideband Wireless
Communication Standard," Proceeding of the IEEE Radio and Wireless
Symposium (RWS2008), Orlando, Florida. Jan. 2224, 2008, pp. 147150.
E. Atalla, I. Bashir, P. T. Balsara, K. Kiasaleh and R. B. Staszewski: "A Practical Step Forward Toward SoftwareDefined Radio
Transmitters,"
Proceeding of the 6^{th} IEEE Dallas Circuits and Systems
Workshop (DCAS '07), Dallas, Texas. Nov. 1516, 2007.
V. Parikh, S. Modi and P. T. Balsara: "Optimum Design of Cascaded Digital Filters in Wideband
Transmitters using Genetic Algorithms," Proceeding of the 6^{th}
IEEE Dallas Circuits and Systems Workshop (DCAS '07), Dallas, Texas.
Nov. 1516, 2007.
I. Syllaios, P. T. Balsara and R. B. Staszewski: "TimeDomain Modeling of a PhaseDomain AllDigital
PhaseLocked Loop for RF Applications,"
Proceedings of the IEEE Custom Integrated
Circuits Conference, San Jose, CA, Sept. 1619, 2007, pp. 861864.
C. K. Singh, N. AlDhahir and P.T. Balsara: "Effect of Wordlength Precision on the Performance of
MIMO Systems,"
Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS),
New Orleans, LA, May 2730, 2007. pp. 25982601.
V. Parikh, P.T. Balsara, O. Eliezer and J. Mehta: "A Low Power and Low Quantization Noise Digital
Modulator for Wireless Transmitters,"
Proceedings of
the IEEE International Conference on Circuits and Systems (ISCAS),
New Orleans, LA, May 2730, 2007, pp. 32753278.
R. Staszewski and P. T. Balsara: "AllDigital PLL with Ultra Fast Settling,"
IEEE Transactions on Circuits and SystemsII, vol. 54, No. 2, Feb. 2007, pp.
181185.
O. Eliezer, I. Bashir, R. B. Staszewski, P. T. Balsara: "Builtin Self Testing of a DRPBased GSM Transmitter,"
Proceedings of the IEEE RFIC Symposium, Honolulu, Hawaii, June 35, 2007, pp.
339342.
V. Parikh, P.T. Balsara, O. Eliezer and J. Mehta: "A Low Area and Low Power Digital BandPass SigmaDelta
Modulator for Wireless Transmitters," Proceedings of the IEEE
International Conference on Circuits and Systems (ISCAS), New
Orleans, LA, May 2730, 2007, pp. 32793282.
C. Singh, S. Honnavara Prasad and P.T. Balsara: "VLSI Architecture for Matrix Inversion using Modified
GramSchmidt based QR Decomposition,"
Proceedings of the 20^{th} IEEE
International Conference on VLSI Design (VLSI '07), Bangalore,
India. Jan. 610, 2007, pp. 836841.
I. Elahi, K. Muhammad, and P. T. Balsara: "IIP2 and DC Offsets in the Presence of
Leakage at LO Frequency," IEEE Transactions on Circuits and SystemsII, vol.
53, No. 8, Aug. 2006, pp. 647651.
M. J. Akhbarizadeh, M. Nourani, DeepakSarathi V., and P. T. Balsara: "A
NonRedundant Ternary CAM Circuit for Network SearchEngines," IEEE
Transactions on VLSI Systems, vol. 14, No. 3, March 2006, pp. 268278.
R.
Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara: "1.3V
20ps TimetoDigital Converter in 90nm CMOS," IEEE Transactions on Circuits and
SystemsII, vol. 53, No. 3, March 2006, pp. 220224.
I. Elahi, K. Muhammad, and P. T. Balsara: "I/Q Mismatch Compensation Using
Adaptive Decorrelation in a LowIF Receiver in 90nm CMOS Process," IEEE Journal
on SolidState Circuits, vol. 41, No. 2, February 2006, pp. 395404.
I. Syllaios, P. T. Balsara, and O. Eliezer: "A Generalized Signal Reconstruction Method for Designing
Interpolation Filters,"
Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS),
Kos, Greece, May 2006, pp. 57685771.
S. Singh, S. Bhoj, D. Balasubramanian, T. Nagda, D. Bhatia and P. T. Balsara: "Generic Network Interfaces for Plug and Play NoC Based
Architecture,"
International Workshop on Applied Reconfigurable Computing (ARC2006),
Delft, The Netherlands, March 13, 2006, Lecture Notes in Computer Science,
Vol. 3985, Reconfigurable Computing: Architectures and Applications,
SpringerVerlag, pp. 287298.
V. Ramakrishnan and P.T. Balsara: "A WideRange HighResolution
Compact CMOS Time to Digital Converter," Proceedings of the
19^{th} IEEE International Conference on VLSI Design (VLSI '06),
Hyderabad, India, January 37, 2006, pp. 197202.
R. Venkatasubramanian and P.T. Balsara: "Implementation of a WideRange,
HighResolution, Compact Time to Digital Converter in 0.5um CMOS
Technology," Chip Design Contest Entry at the 19^{th} IEEE
International Conference on VLSI Design (VLSI '06), Hyderabad,
India, January 37, 2006. Second Prize Winner.
R. Konar, R. Bharadwaj, D. Bhatia and P.T. Balsara: "Exploring Logic Block Granularity in Leakage Tolerant
FPGAs,"
Proceedings of the 19^{th} IEEE International Conference on VLSI
Design (VLSI '06), Hyderabad, India, January 37, 2006, pp. 754757.
R. Bharadwaj, R. Konar, D. Bhatia, and P. T. Balsara: "FPGA Architecture for Standby Power Management," Proceedings of
the IEEE Conference on Field Programmable Technology (FPT),
Singapore, Dec. 1114, 2005, pp. 181188.
R. Staszewski, G. Shriki, and P. T. Balsara: "AllDigital PLL with Ultra Fast Acquisition,"
Proceedings of
the IEEE Asian SolidState Circuits Conference, Hsinchu, Taiwan, Nov. 13,
2005, sec. 117, pp. 289292.
R. B. Staszewski, R. Staszewski, J. Wallberg, T. Jung, J. Koh, CM Hung, J. Koh,
D. Leipold, K. Maggio, and P. T. Balsara: "SoC with an Integrated DSP and a
2.4GHz RF Transmitter," IEEE Transactions on VLSI Systems, vol. 13, No. 11,
November 2005, pp. 12531265.
D. S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh,, and P. T. Balsara: "RipplePrecharge TCAM: A LowPower Solution for Network
Search Engines,"
Proceedings of the IEEE International Conference on Computer Design (ICCD),
San Jose, CA, Oct. 25, 2005, pp. 243248.
R. Venkatasubramanian, and P. T. Balsara: "Very High Precision Vernier Delay Line Based Pulse
Generator,"
Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, October
2005, pp. 225228.
C. Sundaram, P. T. Balsara, S. Vemulapalli, P. Vallur, and O. Eliezer: "Yield Aware Digital Design Methodology For Sub100
Nanometer SOC Designs,"
Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, October
2005, pp. 237240.
R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara: "TimetoDigital Converter for RF Frequency Synthesis in
90nm CMOS,"
Proceeding of the
2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,
Long Beach, CA, June 2005, pp. 473476.
R. B. Staszewski, R. Staszewski, and P. T. Balsara: "VHDL Simulation and Modeling of an AllDigital RF
Transmitter,"
Proceedings of the
5^{th} International Workshop on SoC, Banff, Canada, July 2024,
2005, pp. 233238. Best Paper Award.
R. Staszewski, D. Leipold, and P. T. Balsara: "Direct Frequency Modulation of an
ADPLL for Bluetooth/GSM with Injection Pulling Elimination," IEEE Transactions
on Circuits and SystemsII, vol. 52, No. 6, June 2005, pp. 339343.
M. Chugh, D. Bhatia, and P. T. Balsara: "Design and Implementation of Configurable WCDMA Rake
Receiver Architectures on FPGA,"
Proceedings of the 12^{th}
Reconfigurable Architectures Workshop (RAW 2005), Denver, Colorado,
April 45, 2005. pp. 18.
R. Staszewski, C. Fernando, and P. T. Balsara: "EventDriven Simulation and
Modeling of an RF Oscillator," IEEE Transactions on Circuits and SystemsI,
Vol. 52, No. 4, April 2005, pp. 723732.
R. Staszewski,, and P. T. Balsara: "PhaseDomain AllDigital PhaseLocked Loop,"
IEEE Transactions on Circuits and SystemsII, Vol. 52, No. 3, March 2005, pp.
159163.
R. Bharadwaj, R. Konar, P. T. Balsara, and D. Bhatia: "Exploiting Temporal Idleness to Reduce Leakage Power in
Programmable Architectures
Proceedings of the Asia and South Pacific
Design Automation Conference (ASPDAC), Shanghai, China, Jan. 1821,
2005. pp. 651656
R. Vilangudipitchai, and P. T. Balsara: "Power Switch Network Design for MTCMOS," Proceedings of
the 18^{th} IEEE International Conference on VLSI Design (VLSI '05), Kolkata, India, January 37, 2005. pp. 836839.
NS Nagaraj, W. Hunter, P. T. Balsara and C. Cantrell: "The Impact of Inductance on Transients Affecting Gate
Oxide Reliability,"
Embedded Tutorial, 18^{th} International Conference on VLSI Design (VLSI '05), Kolkata, India, January 37, 2005. pp. 709713.
R. B. Staszewski, K. Muhammad, D. Leipold, CM Hung, YC Ho, J. Wallberg, C.
Fernando, K. Maggio, R. Staszewski, J. Koh, S. John, I. Deng, V. Sarda, O.
Moreira, V. Mayega, R. Katz, O. Friedman, O. Eliezer, and P. T. Balsara:
"AllDigital TX Frequency Synthesizer and DiscreteTime Receiver for Bluetooth
Radio in 130 nm CMOS Process," IEEE Journal of SolidState Circuits, Vol. 39,
No. 12, Dec. 2004, pp. 22782291.
M. J. Akhbarizadeh, M. Nourani, DeepakSarathi V.,, and P. T. Balsara: "PCAM: A Ternary CAM Optimized for Longest Prefix Matching
Tasks,"
Proceedings of the IEEE International Conference on Computer Design (ICCD),
San Jose, CA, Oct. 1113, 2004. pp. 611. Best Paper Award.
R. Vilangudipitchai, and P. T. Balsara: "Decap Aware Sleep Transistor Design," Proceedings of
the IEEE Dallas/CAS Workshop, Richardson, TX, September 27, 2004, pp.
171175.
R. B. Staszewski, J. Wallberg, J. Koh, and P. T. Balsara: "HighSpeed Digital Circuits for a 2.4 GHz AllDigital RF
Frequency Synthesizer in 130nm CMOS,"
Proceedings of the IEEE Dallas/CAS Workshop,
Richardson, TX, September 27, 2004, pp. 167170.
R. B. Staszewski, C. Fernando, and P. T. Balsara: "Eventdriven Simulation and Modeling of an RF Oscillator,"
Proceeding of the
IEEE International Symposium on Circuits and Systems, Vancouver, Canada,
May 2004, pp. 641644.
R. B. Staszewski, CM Hung, Ken Maggio, J. Wallberg, D. Leipold, and P. T. Balsara: "AllDigital PhaseDomain TX Frequency Synthesizer for
Bluetooth Radios in 0.13um CMOS,"
Proceedings of the IEEE International
SolidState Circuits Conference, San Francisco, CA, Feb. 2004, pp.
272273,527.
R. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara: "DigitallyControlled
Oscillator (DCO)Based Architecture in a DeepSubmicron CMOS Process for
Wireless Applications," IEEE Transactions on Circuits and SystemsII, Vol. 50,
No. 11, Nov. 2003, pp. 815828.
R. Staszewski, D. Leipold,, and P. T. Balsara: "JustInTime Gain Estimation of
an RF DigitallyControlled Oscillator for Digital Direct Frequency Modulation,"
IEEE Transactions on Circuits and SystemsII, Vol. 50, No. 11, Nov. 2003, pp.
887892.
R. Staszewski, CM Hung, D. Liepold, and P. T. Balsara: "A First MultiGHz
Digitally Controlled Oscillator for Wireless Applications," IEEE Transactions
on Microwave Theory and Techniques, Vol. 51, No. 11, Nov. 2003, pp. 21542164.
R. Staszewski, D. Leipold, J. Wallberg, and P. T. Balsara: "JustInTime Gain Estimation of an RF DigitallyControlled
Oscillator,"
Proceedings of the
IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2124,
2003, pp. 571574.
R. Staszewski, D. Leipold, CM Hung, and P. T. Balsara: "A First DigitallyControlled Oscillator in a
DeepSubmicron CMOS Process for MultiGHz Wireless Applications,"
Proceedings of the
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,
Philadelphia, PA, June 810, 2003, sec. MO4B2, pp. 8184.
R. Staszewski, K. Muhammad, and P. T. Balsara: "A Constrained Asymmetry LMS
Algorithm for PRML Disk Drive Read Channels," IEEE Transactions on Circuits and
SystemsII: Analog and Digital Signal Processing, Vol. 48, No. 8, August 2001,
pp. 793798.
K. Muhammad, R. Staszewski,, and P. T. Balsara: "Challenges in Integrated CMOS Transceivers for Short
Distance Wireless,"
Proceedings of the Great Lakes VLSI Symposium, 2001 (Invited),
pp. 4550
K. Muhammad, R. Staszewski, and P. T. Balsara: "Speed, Power, Area and Latency
Tradeoffs in Adaptive FIR Filtering for PRML Read Channels," IEEE Transactions
on VLSI Systems, Vol. 9, No. 1, February 2001, pp. 4251.
R. Staszewski, K. Muhammad, and P. T. Balsara: "A 550 Msps 8Tap FIR Digital
Filter for Magnetic Recording Read Channel," IEEE Journal of SolidState
Circuits, Vol. 35, No. 8, August 2000, pp. 12051210.
U. Ko, and P.T. Balsara: "High Performance, Energy Efficient D Flipflop
Circuits," IEEE Transactions on VLSI Systems, Vol. 8, No. 1, February 2000, pp.
9498.
S. S. MahantShetti, P.T. Balsara, and C. Lemonds: "High Performance, Low Power
Array Multiplier using Temporal Tiling," IEEE Transactions on VLSI Systems,
Vol. 7, No. 1, March 1999, pp 121124.
U.Ko, P.T. Balsara, and A. K. Nanda: "Energy Optimization of Multilevel Cache
Architectures for RISC and CISC Processors," IEEE Transactions on VLSI Systems,
Vol. 6, No. 2, June 1998, pp. 299308.
