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BookB. Staszewski and P. T. Balsara: "All-Digital Frequency Synthesizer in Deep-Submicron CMOS," Wiley-Interscience, John Wiley & Sons, Hoboken, New Jersey, Sept. 2006. ISBN 0-471-77255-0.
Selected Journal and Conference PublicationsD. Patil, J. Miller, B. Fahimi, J. M. Miller, B. Fahimi, P. T. Balsara, and V. Galigekere: "A Coil Detection System for Dynamic Wireless Charging of Electric Vehicle, " to appear in IEEE Transactions on Transportation Electrification. P. C. Buck, B. Fahimi, and P. T. Balsara: "A Phase Current Peak Prediction Technique to Increase the Output Power of Switched Reluctance Generators for Wind Turbines," Proceedings of the IEEE Energy Conversion Congress and Expo (ECCE 2019), Baltimore, MD, 2019, pp. 5244-5250. S. Arora, P.T. Balsara, and D. K. Bhatia: "Input-Output Linearization of a Boost Converter with Constant Power Load," IEEE Transactions on Power Electronics, Vol. 34, No. 1, January 2019, pp. 815-825. L. Maharjan, E. Bostanci, S. Wang, E. Cosoroaba, W. Cai, F. Yi, P. Shamsi, W. Wang, L. Gu, M. Luo, N. Rahman, M. McDonough, C. Lin, J. Hearron, C. Narvaez, M. Wu, A. Isfahani, Y. Li, G. Rao, M. Moallem, P.T. Balsara, and B. Fahimi: "Comprehensive Report on Design and Development of a 100kW DSSRM," IEEE Transactions on Transportation Electrification, Vol. 4, No. 4, December 2018, pp. 835-856. S. Arora, D. K. Bhatia, P.T. Balsara, and P. Buck: "A Novel Digital Architecture for Gain and Phase Measurements in a PWM Controller," Proceedings of the IEEE Dallas Circuits and Systems Conference (DCAS'18), Richardson, Texas. Nov. 12, 2018, pp. 1-4. D. Patil, B. Fahimi, J. M. Miller, M. K. McDonough, and P. T. Balsara: "Wireless Power Transfer for Vehicular Application: Overview and Challenges," IEEE Transactions on Transportation Electrification, Vol. 4, No. 1, March 2018, pp. 3-37. V. Paduvalli, R. Taylor, L.R. Hunt, and P. T. Balsara: "Mitigation of Positive Zero Effect on Non-Minimum Phase Boost DC-DC Converters," IEEE Transactions on Industrial Electronics, Vol. 65, No. 5, May 2018, pp. 4125-4134. A. A. Thulasi, D.K. Bhatia, P.T. Balsara, and S. Prasad: "Portable Impedance Measurement Device for Sweat Based Glucose Detection," Proceedings of the International Conference on Wearable and Implantable Body Sensor Networks (BSN 2017), Eindhoven, The Netherlands, May 9-12, 2017. S. R. Srinivasan and P.T. Balsara: "A Hybrid DAC Switching Technique for SAR ADCs," Analog Integrated Circuits and Signal Processing, Vol. 92, No. 2, August 2017, pp. 179-187. I. Bashir, B. Staszewski, and P. T. Balsara, "Numerical Model of an Injection Locked Wideband Frequency Modulator for Polar Transmitters," IEEE Transactions on Microwave Theory and Techniques Vol. 65, No. 5, May 2017, pp. 1914-192. V. Paduvalli, R. Taylor, and P. T. Balsara: "Analysis of Zeros in Boost DC-DC Converter: State Diagram Approach," IEEE Transactions on Circuits and Systems II, Vol. 64, No. 5, May 2017, pp. 550-554. E. Atalla, F. Zhang, P. T. Balsara, A. Bellaouar, S. Ba, and K. Kiasaleh: "Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach," IEEE Transactions on Circuits and Systems - I, Vol. 64, No. 2, 2017, pp. 347-359. S. Arora, P.T. Balsara, and D. K. Bhatia: "Effect of Sampling Time and Sampling Instant on the Frequency Response of a Boost Converter," Proceedings of the 42nd IEEE Industrial Electronics Conference (IECON2016), Florence, Italy, October 24-27, 2016. Student Forum Best Paper and Presentation Award I. Bashir, B. Staszewski, O. Eliezer, and P. T. Balsara, "A Wideband Digital-to-Frequency Converter with BIST Mechanism for Self-Interference Mitigation," Journal of Electronic Testing, Theory and Applications (Springer), Vol. 32, No. 4, 2016, pp. 437-445. V. Paduvalli, R. Taylor, L.R. Hunt, and P. T. Balsara: "Input Output Linearization with Non-Minimum Phase Boost DC-DC Converters," IEICE Nonlinear Theory and Its Applications (NOLTA) Journal, Vol. 7, No. 3, July 2016, pp. 419-429. I. Bashir, B. Staszewski, and P. T. Balsara, "A Digitally Controlled Injection Locked Oscillator with Fine Frequency Resolution," IEEE Journal on Solid-State Circuits, vol. 51, no. 6, June 2016, pp. 1347-1360. S. K. Manohar and P.T. Balsara: "High Efficiency DCM Buck Converter with Dynamic Logic Based Adaptive Switch-Time Control," Analog Integrated Circuits and Signal Processing 84, 3, September 2015, pp. 455-469. S. K. Manohar, L.R. Hunt, P.T. Balsara, D.K. Bhatia, V.V. Paduvalli: "Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter," IEEE Transactions on Circuits and Systems - I, vol. 62, no. 9, September 2015, pp. 2351-2360. S. Modi, P. T. Balsara, and O. Eliezer: "Envelope Tracking using Transient Waveform Shaping Switching Supply Modulation," International Journal of Circuit Theory and Applications, vol. 43, no. 5, May 2015, pp. 656-674. S. Arora, P.T. Balsara, D. K. Bhatia, R. J. Taylor, and L. R. Hunt: "Gain and Phase (GAP) Measurement Device," Proceedings of the 30th Annual IEEE Applied Power Electronics Conference and Exposition (APEC2015), Charlotte, NC. R. Venkatasubramanian, S. K. Manohar and P. T. Balsara: "Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency," IEEE Transactions on Nanotechnology, vol. 14, no. 1, January 2015, pp.140-151. A. Awasthi, R. Guttal, N. Al-Dhahir and P. T. Balsara: "Complex QR Decomposition using Fast Plane Rotations for MIMO Applications," IEEE Communications Letters, vol. 18, no. 10, October 2014, pp. 1743-1746. S. R. Srinivasan and P.T. Balsara: "Energy-efficient sub-DAC merging scheme for variable resolution SAR ADC," IET Electronics Letters, vol. 50, no. 20, September 2014, pp. 1421-1423. S. Modi, N. Yanduru, and P.T. Balsara: "Efficiency Improvement of Doherty Power Amplifier using Supply Switching and Gate Bias Modulation," 15th Annual IEEE Wireless and Microwave Technology Conference (WAMICON2014), Cocoa Beach, FL, April 13-15, 2014. E. Atalla, F. Zhang, A. Bellaouar, and P. T. Balsara: "Estimation of Passive Mixer Output Bandwidth Using Switched-Capacitor Techniques," 2013 IEEE Custom Integrated Circuits Conference (CICC), Sept. 22-25, 2013, pp. 1-4. S. K. Manohar and P.T. Balsara: "94.6% Peak Efficiency DCM Buck Converter with Fast Adaptive Dead-Time Control," 39th European Solid-State Circuits Conference (ESSCIRC), Bucharest, Romania, Sept 16-20, 2013, pp. 153-156. E. Atalla, A. Bellaouar, and P. T. Balsara: "IIP2 Requirements in 4G LTE Handset Receivers," 2013 IEEE Midwest Circuits and Systems Symposium (MWCAS), Aug. 4-7, 2013, pp. 1132-1135 R. Venkatasubramanian, S. K. Manohar and P. T. Balsara: "NEM Relay Based Sequential Logic Circuits for Low Power Design," IEEE Transactions on Nanotechnology, vol. 12, no. 3, May 2013, pp. 386-398. I. Syllaios and P. T. Balsara: "Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops," IEEE Transactions on Circuits and Systems-I, vol. 59, no. 11, November 2012, pp. 2495-2506. S. Modi and P.T. Balsara: "Reduced Bandwidth Class H Supply Modulation for Wideband RF Power Amplifiers " Proceedings of the 13th Annual IEEE Wireless and Microwave Technology Conference (WAMICON2012), Cocoa Beach, FL, April 16-17, 2012, pp. 1-7. J. Mehta, R. B. Staszewski, G. Feygin, O. Eliezer, M. Frechette, and P.T. Balsara: "Mismatch Considerations in an RF-DAC Design for a Digital Polar EDGE Transmitter," Proceedings of IEEE International Symposium on Radio-Frequency Integration Technology (RFIT2011), Beijing, China. Nov. 30 - Dec. 2, 2011, pp. 169-172. Venkatasubramanian, S. K. Manohar and P. T. Balsara: "Improving Performance of NEM Relay Logic Circuits using Integrated Charge-Boosting Flip-Flop," Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2011. I. Syllaios and P.T. Balsara: "Multi-Clock Domain Analysis and Modeling of All-Digital Frequency Synthesizers," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 153-156. I. Bashir, R. B. Staszewski, O. Eliezer, B. Banerjee and P. T. Balsara: "A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter," IEEE Journal on Solid-State Circuits, vol. 46, no. 2, February 2011, pp. 403-415 V.K.K. Srinivasan, C. K. Singh and P. T. Balsara: "A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder," IEEE Transactions on VLSI, vol. 18, No. 9, September 2010, pp. 11372-1376. S. Modi, S. Askari, S. K. Manohar, N. Yanduru, P.T. Balsara and M. Nourani: "Automated GmC Filter Design: A Case Study in Accelerated Reuse of Analog Circuit Design," Proceedings of the 9th IEEE Dallas Circuits and Systems Workshop (DCAS '0), Richardson, Texas. Oct. 17-18, 2010. I. Syllaios, P. T. Balsara and R. B. Staszewski: "Recombination of Envelope and Phase Paths in Wideband Polar Transmitters," IEEE Transactions on Circuits and Systems-I, vol. 57, No. 8, August 2010, pp. 1891-1904. J. Mehta, V. Zoicas, O. E. Eliezer, R. B. Staszewski, S. Rezeq, M. Entezari and P.T. Balsara: "An Efficient Linearization Scheme for a Digital Polar Edge Transmitter," IEEE Transactions on Circuits and Systems-II, vol. 57, No. 3, March 2010, pp. 193-197. V. Parikh, P. T. Balsara and O. E. Eliezer: "All Digital Quadrature Modulator for Wideband Wireless Transmitters," IEEE Transactions on Circuits and Systems-I, vol. 56, No. 11, November 2009, pp. 2487-2497. O. Eliezer, B. Staszewski, S. Bhatara, I. Bashir, and P. T. Balsara: "A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers," IEEE Journal on Solid-State Circuits, vol. 44, No. 5, May 2009, pp. 1436-1453. I. Elahi, K. Muhammad, and P. T. Balsara: "Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation," IEEE Transactions on Circuits and System-II, vol. 56, No. 1, January 2009, pp. 86-90. S. Modi, S. Kanigere, O. Eliezer and P. T. Balsara: "Limited Bandwidth Envelope Follower for Improving Efficiency of Broadband Linear Power Amplifier," Proceeding of the 7th IEEE Dallas Circuits and Systems Workshop (DCAS'08), Richardson, Texas. Oct. 19-20, 2008, pp. 66-69 I. Syllaios, P. T. Balsara and R. B. Staszewski: "Time-Domain Modeling of a Phase-Domain All-Digital PLL," IEEE Transactions on Circuits and Systems-II, vol. 5, No. 6, June 2008, pp. 601-605. V. Parikh, P. T. Balsara and O. Eliezer: "A Fully Digital Transmitter Architecture for Wideband Wireless Communication Standard," Proceeding of the IEEE Radio and Wireless Symposium (RWS2008), Orlando, Florida. Jan. 22-24, 2008, pp. 147-150. E. Atalla, I. Bashir, P. T. Balsara, K. Kiasaleh and R. B. Staszewski: "A Practical Step Forward Toward Software-Defined Radio Transmitters," Proceeding of the 6th IEEE Dallas Circuits and Systems Workshop (DCAS '07), Dallas, Texas. Nov. 15-16, 2007. V. Parikh, S. Modi and P. T. Balsara: "Optimum Design of Cascaded Digital Filters in Wideband Transmitters using Genetic Algorithms," Proceeding of the 6th IEEE Dallas Circuits and Systems Workshop (DCAS '07), Dallas, Texas. Nov. 15-16, 2007. I. Syllaios, P. T. Balsara and R. B. Staszewski: "Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications," Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 16-19, 2007, pp. 861-864. C. K. Singh, N. Al-Dhahir and P.T. Balsara: "Effect of Word-length Precision on the Performance of MIMO Systems," Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS), New Orleans, LA, May 27-30, 2007. pp. 2598-2601. V. Parikh, P.T. Balsara, O. Eliezer and J. Mehta: "A Low Power and Low Quantization Noise Digital Modulator for Wireless Transmitters," Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS), New Orleans, LA, May 27-30, 2007, pp. 3275-3278. R. Staszewski and P. T. Balsara: "All-Digital PLL with Ultra Fast Settling," IEEE Transactions on Circuits and Systems-II, vol. 54, No. 2, Feb. 2007, pp. 181-185. O. Eliezer, I. Bashir, R. B. Staszewski, P. T. Balsara: "Built-in Self Testing of a DRP-Based GSM Transmitter," Proceedings of the IEEE RFIC Symposium, Honolulu, Hawaii, June 3-5, 2007, pp. 339-342. V. Parikh, P.T. Balsara, O. Eliezer and J. Mehta: "A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters," Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS), New Orleans, LA, May 27-30, 2007, pp. 3279-3282. C. Singh, S. Honnavara Prasad and P.T. Balsara: "VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition," Proceedings of the 20th IEEE International Conference on VLSI Design (VLSI '07), Bangalore, India. Jan. 6-10, 2007, pp. 836-841. I. Elahi, K. Muhammad, and P. T. Balsara: "IIP2 and DC Offsets in the Presence of Leakage at LO Frequency," IEEE Transactions on Circuits and Systems-II, vol. 53, No. 8, Aug. 2006, pp. 647-651. M. J. Akhbarizadeh, M. Nourani, Deepak-Sarathi V., and P. T. Balsara: "A Non-Redundant Ternary CAM Circuit for Network Search-Engines," IEEE Transactions on VLSI Systems, vol. 14, No. 3, March 2006, pp. 268-278. R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara: "1.3V 20ps Time-to-Digital Converter in 90nm CMOS," IEEE Transactions on Circuits and Systems-II, vol. 53, No. 3, March 2006, pp. 220-224. I. Elahi, K. Muhammad, and P. T. Balsara: "I/Q Mismatch Compensation Using Adaptive Decorrelation in a Low-IF Receiver in 90nm CMOS Process," IEEE Journal on Solid-State Circuits, vol. 41, No. 2, February 2006, pp. 395-404. I. Syllaios, P. T. Balsara, and O. Eliezer: "A Generalized Signal Reconstruction Method for Designing Interpolation Filters," Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS), Kos, Greece, May 2006, pp. 5768-5771. S. Singh, S. Bhoj, D. Balasubramanian, T. Nagda, D. Bhatia and P. T. Balsara: "Generic Network Interfaces for Plug and Play NoC Based Architecture," International Workshop on Applied Reconfigurable Computing (ARC2006), Delft, The Netherlands, March 1-3, 2006, Lecture Notes in Computer Science, Vol. 3985, Reconfigurable Computing: Architectures and Applications, Springer-Verlag, pp. 287-298. V. Ramakrishnan and P.T. Balsara: "A Wide-Range High-Resolution Compact CMOS Time to Digital Converter," Proceedings of the 19th IEEE International Conference on VLSI Design (VLSI '06), Hyderabad, India, January 3-7, 2006, pp. 197-202. R. Venkatasubramanian and P.T. Balsara: "Implementation of a Wide-Range, High-Resolution, Compact Time to Digital Converter in 0.5um CMOS Technology," Chip Design Contest Entry at the 19th IEEE International Conference on VLSI Design (VLSI '06), Hyderabad, India, January 3-7, 2006. Second Prize Winner. R. Konar, R. Bharadwaj, D. Bhatia and P.T. Balsara: "Exploring Logic Block Granularity in Leakage Tolerant FPGAs," Proceedings of the 19th IEEE International Conference on VLSI Design (VLSI '06), Hyderabad, India, January 3-7, 2006, pp. 754-757. R. Bharadwaj, R. Konar, D. Bhatia, and P. T. Balsara: "FPGA Architecture for Standby Power Management," Proceedings of the IEEE Conference on Field Programmable Technology (FPT), Singapore, Dec. 11-14, 2005, pp. 181-188. R. Staszewski, G. Shriki, and P. T. Balsara: "All-Digital PLL with Ultra Fast Acquisition," Proceedings of the IEEE Asian Solid-State Circuits Conference, Hsinchu, Taiwan, Nov. 1-3, 2005, sec. 11-7, pp. 289-292. R. B. Staszewski, R. Staszewski, J. Wallberg, T. Jung, J. Koh, C-M Hung, J. Koh, D. Leipold, K. Maggio, and P. T. Balsara: "SoC with an Integrated DSP and a 2.4GHz RF Transmitter," IEEE Transactions on VLSI Systems, vol. 13, No. 11, November 2005, pp. 1253-1265. D. S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh,, and P. T. Balsara: "Ripple-Precharge TCAM: A Low-Power Solution for Network Search Engines," Proceedings of the IEEE International Conference on Computer Design (ICCD), San Jose, CA, Oct. 2-5, 2005, pp. 243-248. R. Venkatasubramanian, and P. T. Balsara: "Very High Precision Vernier Delay Line Based Pulse Generator," Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, October 2005, pp. 225-228. C. Sundaram, P. T. Balsara, S. Vemulapalli, P. Vallur, and O. Eliezer: "Yield Aware Digital Design Methodology For Sub-100 Nanometer SOC Designs," Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, October 2005, pp. 237-240. R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara: "Time-to-Digital Converter for RF Frequency Synthesis in 90nm CMOS," Proceeding of the 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Long Beach, CA, June 2005, pp. 473-476. R. B. Staszewski, R. Staszewski, and P. T. Balsara: "VHDL Simulation and Modeling of an All-Digital RF Transmitter," Proceedings of the 5th International Workshop on SoC, Banff, Canada, July 20-24, 2005, pp. 233-238. Best Paper Award. R. Staszewski, D. Leipold, and P. T. Balsara: "Direct Frequency Modulation of an ADPLL for Bluetooth/GSM with Injection Pulling Elimination," IEEE Transactions on Circuits and Systems-II, vol. 52, No. 6, June 2005, pp. 339-343. M. Chugh, D. Bhatia, and P. T. Balsara: "Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA," Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), Denver, Colorado, April 4-5, 2005. pp. 1-8. R. Staszewski, C. Fernando, and P. T. Balsara: "Event-Driven Simulation and Modeling of an RF Oscillator," IEEE Transactions on Circuits and Systems-I, Vol. 52, No. 4, April 2005, pp. 723-732. R. Staszewski,, and P. T. Balsara: "Phase-Domain All-Digital Phase-Locked Loop," IEEE Transactions on Circuits and Systems-II, Vol. 52, No. 3, March 2005, pp. 159-163. R. Bharadwaj, R. Konar, P. T. Balsara, and D. Bhatia: "Exploiting Temporal Idleness to Reduce Leakage Power in Programmable Architectures Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, Jan. 18-21, 2005. pp. 651-656 R. Vilangudipitchai, and P. T. Balsara: "Power Switch Network Design for MTCMOS," Proceedings of the 18th IEEE International Conference on VLSI Design (VLSI '05), Kolkata, India, January 3-7, 2005. pp. 836-839. NS Nagaraj, W. Hunter, P. T. Balsara and C. Cantrell: "The Impact of Inductance on Transients Affecting Gate Oxide Reliability," Embedded Tutorial, 18th International Conference on VLSI Design (VLSI '05), Kolkata, India, January 3-7, 2005. pp. 709-713. R. B. Staszewski, K. Muhammad, D. Leipold, C-M Hung, Y-C Ho, J. Wallberg, C. Fernando, K. Maggio, R. Staszewski, J. Koh, S. John, I. Deng, V. Sarda, O. Moreira, V. Mayega, R. Katz, O. Friedman, O. Eliezer, and P. T. Balsara: "All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130 nm CMOS Process," IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, Dec. 2004, pp. 2278-2291. M. J. Akhbarizadeh, M. Nourani, Deepak-Sarathi V.,, and P. T. Balsara: "PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks," Proceedings of the IEEE International Conference on Computer Design (ICCD), San Jose, CA, Oct. 11-13, 2004. pp. 6-11. Best Paper Award. R. Vilangudipitchai, and P. T. Balsara: "Decap Aware Sleep Transistor Design," Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, September 27, 2004, pp. 171-175. R. B. Staszewski, J. Wallberg, J. Koh, and P. T. Balsara: "High-Speed Digital Circuits for a 2.4 GHz All-Digital RF Frequency Synthesizer in 130nm CMOS," Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, September 27, 2004, pp. 167-170. R. B. Staszewski, C. Fernando, and P. T. Balsara: "Event-driven Simulation and Modeling of an RF Oscillator," Proceeding of the IEEE International Symposium on Circuits and Systems, Vancouver, Canada, May 2004, pp. 641-644. R. B. Staszewski, C-M Hung, Ken Maggio, J. Wallberg, D. Leipold, and P. T. Balsara: "All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13um CMOS," Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, Feb. 2004, pp. 272-273,527. R. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara: "Digitally-Controlled Oscillator (DCO)-Based Architecture in a Deep-Submicron CMOS Process for Wireless Applications," IEEE Transactions on Circuits and Systems-II, Vol. 50, No. 11, Nov. 2003, pp. 815-828. R. Staszewski, D. Leipold,, and P. T. Balsara: "Just-In-Time Gain Estimation of an RF Digitally-Controlled Oscillator for Digital Direct Frequency Modulation," IEEE Transactions on Circuits and Systems-II, Vol. 50, No. 11, Nov. 2003, pp. 887-892. R. Staszewski, C-M Hung, D. Liepold, and P. T. Balsara: "A First Multi-GHz Digitally Controlled Oscillator for Wireless Applications," IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 11, Nov. 2003, pp. 2154-2164. R. Staszewski, D. Leipold, J. Wallberg, and P. T. Balsara: "Just-In-Time Gain Estimation of an RF Digitally-Controlled Oscillator," Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 21-24, 2003, pp. 571-574. R. Staszewski, D. Leipold, C-M Hung, and P. T. Balsara: "A First Digitally-Controlled Oscillator in a Deep-Submicron CMOS Process for Multi-GHz Wireless Applications," Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Philadelphia, PA, June 8-10, 2003, sec. MO4B-2, pp. 81-84. R. Staszewski, K. Muhammad, and P. T. Balsara: "A Constrained Asymmetry LMS Algorithm for PRML Disk Drive Read Channels," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No. 8, August 2001, pp. 793-798. K. Muhammad, R. Staszewski,, and P. T. Balsara: "Challenges in Integrated CMOS Transceivers for Short Distance Wireless," Proceedings of the Great Lakes VLSI Symposium, 2001 (Invited), pp. 45-50 K. Muhammad, R. Staszewski, and P. T. Balsara: "Speed, Power, Area and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read Channels," IEEE Transactions on VLSI Systems, Vol. 9, No. 1, February 2001, pp. 42-51. R. Staszewski, K. Muhammad, and P. T. Balsara: "A 550 Msps 8-Tap FIR Digital Filter for Magnetic Recording Read Channel," IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August 2000, pp. 1205-1210. U. Ko, and P.T. Balsara: "High Performance, Energy Efficient D Flip-flop Circuits," IEEE Transactions on VLSI Systems, Vol. 8, No. 1, February 2000, pp. 94-98. S. S. Mahant-Shetti, P.T. Balsara, and C. Lemonds: "High Performance, Low Power Array Multiplier using Temporal Tiling," IEEE Transactions on VLSI Systems, Vol. 7, No. 1, March 1999, pp 121-124. U.Ko, P.T. Balsara, and A. K. Nanda: "Energy Optimization of Multilevel Cache Architectures for RISC and CISC Processors," IEEE Transactions on VLSI Systems, Vol. 6, No. 2, June 1998, pp. 299-308.
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