VLSI Tutorial Website
Prof. Carl Sechen
Office: ECSN 4.902
Email: Carl.Sechen@utdallas.edu
Setup
HDL
Verilog - Hardware Description Language
Logic Synthesis
Library_Complier - Library generation tool by Synopsys
Design_Vision - HDL to gate level synthesis tool by Synopsys
Transistor Level Simulation
HSPICE - Simulation Program with Integrated Circuit Emphasis
Cadence Tools
Placement and Routing
Encounter - Automatic VLSI placement and routing tool by Cadence
Timing Analysis
PrimeTime - Static Timing Analysis (STA) timer by Synopsys
Last update:
April 13, 2021 17:57:12