Skip to content

Static Timing Analysis (STA) - PrimeTime by Synopsys

PrimeTime is a Static Timing Analysis (STA) tool from Synopsys.

This is a simple description to use PrimeTime for VLSI class project.

In Project #6, you will learn to find critical path using PrimeTime from your synthesized Verilog code.

Go to your PrimeTime working directory first.

cd ~/cad/primetime

The folder should contain the following files

  • ndl.v # a sample synthesized verilog netlist
  • Primetime.script
  • library.lib
  • library.db
  • Variables1

1) Gedit variables1 file by typing:

gedit variables1 &

2) You will see that the setup is currently

library file    -> libraray.db
Verilog_file    -> ndl.v
driving_cell    -> inv
clock_pin_name  -> ck
clock_period    -> 20ns
reset_pin_name  -> reset

3) These variables are set by looking at the Verilog file (ndl.v )and the .lib file (library.db).

4) So you need to modify them based on your Verilog netlist, .lib and .db that you generate in project 5.

5) Source the synopsys profile before running primetype

. /proj/cad/startup/profile.synopsys_2018

6) Now you can run Primetime by typing

pt_shell -f primetime.script

Tips:

  • The verilog file imported into PrimeTime must be a flattened one.
  • Run the design first at an arbitrary clock period, the tool will report the slack as positive or negative.
  • If the slack is negative you can fix it by increasing your clock period to make it positive.
  • The tool also reports the power consumption.
Last update: May 5, 2022 23:25:32